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authorSteve Reinhardt <stever@eecs.umich.edu>2006-12-12 09:58:40 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2006-12-12 09:58:40 -0800
commit6c8c86f2f97913788237f763d4810ab12730ca60 (patch)
tree5b4754b2e0cf43b84b99ec77d0ed950dc46a02fb /src/arch/isa_parser.py
parenta7ea4885cebed69a56bb230955484fabb23ca986 (diff)
downloadgem5-6c8c86f2f97913788237f763d4810ab12730ca60.tar.xz
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
Diffstat (limited to 'src/arch/isa_parser.py')
-rwxr-xr-xsrc/arch/isa_parser.py25
1 files changed, 13 insertions, 12 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 6504c7b32..a96622d4a 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1180,15 +1180,16 @@ class IntRegOperand(Operand):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to read integer register as FP')
if (self.size == self.dflt_size):
- return '%s = xc->readIntReg(this, %d);\n' % \
+ return '%s = xc->readIntRegOperand(this, %d);\n' % \
(self.base_name, self.src_reg_idx)
elif (self.size > self.dflt_size):
- int_reg_val = 'xc->readIntReg(this, %d)' % (self.src_reg_idx)
+ int_reg_val = 'xc->readIntRegOperand(this, %d)' % \
+ (self.src_reg_idx)
if (self.is_signed):
int_reg_val = 'sext<%d>(%s)' % (self.dflt_size, int_reg_val)
return '%s = %s;\n' % (self.base_name, int_reg_val)
else:
- return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
+ return '%s = bits(xc->readIntRegOperand(this, %d), %d, 0);\n' % \
(self.base_name, self.src_reg_idx, self.size-1)
def makeWrite(self):
@@ -1201,7 +1202,7 @@ class IntRegOperand(Operand):
wb = '''
{
%s final_val = %s;
- xc->setIntReg(this, %d, final_val);\n
+ xc->setIntRegOperand(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_ctype, final_val, self.dest_reg_idx)
return wb
@@ -1227,13 +1228,13 @@ class FloatRegOperand(Operand):
bit_select = 0
width = 0;
if (self.ctype == 'float'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 32;
elif (self.ctype == 'double'):
- func = 'readFloatReg'
+ func = 'readFloatRegOperand'
width = 64;
else:
- func = 'readFloatRegBits'
+ func = 'readFloatRegOperandBits'
if (self.ctype == 'uint32_t'):
width = 32;
elif (self.ctype == 'uint64_t'):
@@ -1259,18 +1260,18 @@ class FloatRegOperand(Operand):
width = 0
if (self.ctype == 'float'):
width = 32
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'double'):
width = 64
- func = 'setFloatReg'
+ func = 'setFloatRegOperand'
elif (self.ctype == 'uint32_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 32
elif (self.ctype == 'uint64_t'):
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
width = 64
else:
- func = 'setFloatRegBits'
+ func = 'setFloatRegOperandBits'
final_ctype = 'uint%d_t' % self.dflt_size
if (self.size != self.dflt_size and self.is_signed):
final_val = 'sext<%d>(%s)' % (self.size, self.base_name)