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| author | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 21:51:44 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2007-03-07 21:51:44 -0500 |
| commit | 87fb0eb8de8bf66dfae5fc2d069cd17f420fc163 (patch) | |
| tree | c7e3f1c653202f9d920eb740bb6dffa5ebd8df5e /src/arch/isa_parser.py | |
| parent | 2f7a4e1d1b4ab44c5a1d97eaae6ff89fd100a0a9 (diff) | |
| download | gem5-87fb0eb8de8bf66dfae5fc2d069cd17f420fc163.tar.xz | |
I missed a couple of WithEffects, this should do it
--HG--
extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 9b63c8842..21860a2e1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1368,7 +1368,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx + base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: @@ -1378,7 +1378,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscRegOperandWithEffect(this, %s, %s);\n' % \ + wb = 'xc->setMiscRegOperand(this, %s, %s);\n' % \ (self.dest_reg_idx, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name |