diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-26 20:22:23 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-26 20:22:23 -0400 |
| commit | e441be1b82171651308c22eac01c854e7813c2dd (patch) | |
| tree | 402687b2dea1845372075ff8b66b25a108026ad5 /src/arch/isa_parser.py | |
| parent | 93b3176d4e72813bc64340eb534eb280f68764e1 (diff) | |
| download | gem5-e441be1b82171651308c22eac01c854e7813c2dd.tar.xz | |
Change the default function from setMiscRegWithEffect to setMiscReg
--HG--
extra : convert_revision : bedf422d51a52b009390b1e94f5330f752be2b87
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index b235398f1..6504c7b32 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand): def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to write control register as FP') - wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name) + wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name) wb += 'if (traceData) { traceData->setData(%s); }' % \ self.base_name return wb |