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| author | Gabe Black <gabeblack@google.com> | 2019-10-18 17:08:03 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-12-17 23:17:28 +0000 |
| commit | 7a70cbad802d76b0321d8ec070f72d2f48a3ae11 (patch) | |
| tree | 8fb32c22478842ddb6e5900d1c6734aaef7c8766 /src/arch/micro_asm.py | |
| parent | cec93b49359eec5f53dd8c201dc33892e9e376e1 (diff) | |
| download | gem5-7a70cbad802d76b0321d8ec070f72d2f48a3ae11.tar.xz | |
fastmodel: Add an address translation mechanism to the ThreadContext.
This will be used by the TLB to do the actual translation.
Unfortunately there isn't a great way to tell what translation type to
use, so we just go through all of them for now. The ARM subclass might
specialize and figure out which address spaces to use based on control
register state.
Change-Id: Id1fcad66554acf9d69af683917b3c2834f825da0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22118
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/micro_asm.py')
0 files changed, 0 insertions, 0 deletions