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authorGabe Black <gblack@eecs.umich.edu>2007-05-31 13:52:48 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-05-31 13:52:48 +0000
commit62fde97bb2e40002e59d0185db419f6f72643a6f (patch)
treedb70e9653165a534107b12d4506f06e9f29dc7d3 /src/arch/micro_asm_test.py
parent7860c045e2a87a4e63b7d542a63a30da934ac6dd (diff)
downloadgem5-62fde97bb2e40002e59d0185db419f6f72643a6f.tar.xz
Early micro assembler
src/arch/micro_asm.py: Micro assembler src/arch/micro_asm_test.py: Test script for the micro assembler. This probably should go somewhere else eventually. --HG-- extra : convert_revision : 277fdadec94763ae657f55f501704693b81e0015
Diffstat (limited to 'src/arch/micro_asm_test.py')
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diff --git a/src/arch/micro_asm_test.py b/src/arch/micro_asm_test.py
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+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from micro_asm import MicroAssembler, Macroop, Rom
+
+class Bah(object):
+ def __init__(self):
+ self.mnemonic = "bah"
+
+class Bah_Tweaked(object):
+ def __init__(self):
+ self.mnemonic = "bah_tweaked"
+
+class Hoop(object):
+ def __init__(self, first_param, second_param):
+ self.mnemonic = "hoop_%s_%s" % (first_param, second_param)
+ def __str__(self):
+ return "%s" % self.mnemonic
+
+class Dah(object):
+ def __init__(self):
+ self.mnemonic = "dah"
+
+microops = {
+ "bah": Bah,
+ "hoop": Hoop,
+ "dah": Dah
+}
+
+class TestMacroop(Macroop):
+ def tweak(self):
+ microops["bah"] = Bah_Tweaked
+ def untweak(self):
+ microops["bah"] = Bah
+
+ def __init__(self, name):
+ super(TestMacroop, self).__init__(name)
+ self.directives = {
+ "tweak": self.tweak,
+ "untweak": self.untweak
+ }
+
+assembler = MicroAssembler(TestMacroop, microops, Rom('main ROM'))
+
+testAssembly = '''
+def rom {
+ goo: bah
+ extern la: hoop 4*8, "a"
+};
+
+def macroop squishy {
+ .tweak
+ bah
+ .untweak
+ bah
+ dah
+ .tweak
+};
+
+def macroop squashy {
+ bah
+};
+
+def macroop (bar);
+'''
+assembler.assemble(testAssembly)