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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-12-31 15:30:50 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-12-31 15:30:50 -0500 |
| commit | cc07dcf02654267227d9de6ae0898d39d5ea5438 (patch) | |
| tree | 1bec0ecf7c702aab29993e59ca0a496716b225f4 /src/arch/mips/BISystem.py | |
| parent | 1261f1d8db6134d47ccf27bb9b2bbb275deb6b84 (diff) | |
| download | gem5-cc07dcf02654267227d9de6ae0898d39d5ea5438.tar.xz | |
MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.
The MIPS ISA object expects to be constructed with a CPU pointer it uses to
look at other thread contexts and allow them to be manipulated with control
registers. Unfortunately, that differs from all the other ISA classes and
would complicate their implementation.
This change makes the event constructor use a CPU pointer pulled out of the
thread context passed to setMiscReg instead.
Diffstat (limited to 'src/arch/mips/BISystem.py')
0 files changed, 0 insertions, 0 deletions