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author | Gabe Black <gabeblack@google.com> | 2017-04-27 20:47:10 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2017-05-06 20:49:10 +0000 |
commit | 306dea1eb84b9a2076adb626c269d796d0e4bc10 (patch) | |
tree | a701cb21532b43d84fdffff0b2308036d8ffc21a /src/arch/mips/MipsISA.py | |
parent | 8020c689f9d9c77585ef9c5f8c627f1f2a7368f8 (diff) | |
download | gem5-306dea1eb84b9a2076adb626c269d796d0e4bc10.tar.xz |
config: Remove support for CPU aliases.
This was added for backwards compatability, but it adds a decent amount
of complexity.
The table below shows what CPU class name to use in place of a given
alias.
+==========+========================================================+
| Alias | CPU class |
+==========+========================================================+
| timing | TimingSimpleCPU |
| atomic | AtomicSimpleCPU |
| minor | MinorCPU |
| detailed | DrivO3CPU |
| kvm | ArmKvmCPU, ArmV8KvmCPU or X86KvmCPU, depending on arch |
| trace | TraceCPU |
+==========+========================================================+
Change-Id: I251c4f64b7869c6b64dd25b36967ae240f01ef08
Reviewed-on: https://gem5-review.googlesource.com/2940
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/mips/MipsISA.py')
0 files changed, 0 insertions, 0 deletions