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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-14 06:24:47 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-14 06:24:47 -0500 |
| commit | 5f7879a9352985775abef9515e216591a2e3e39d (patch) | |
| tree | 3aa829a03969e0694f914e7e28c597504956a59c /src/arch/mips/MipsTLB.py | |
| parent | bfdd2f379b89654b15f8634d405666f623d336f2 (diff) | |
| download | gem5-5f7879a9352985775abef9515e216591a2e3e39d.tar.xz | |
Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world
--HG--
extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10
Diffstat (limited to 'src/arch/mips/MipsTLB.py')
| -rw-r--r-- | src/arch/mips/MipsTLB.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index b2735d0e7..d06a0e7dd 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -39,19 +39,19 @@ class MipsTLB(SimObject): size = Param.Int("TLB size") class MipsDTB(MipsTLB): - type = 'DTB' + type = 'MipsDTB' cxx_namespace = 'MipsISA' cxx_class = 'DTB' size = 64 class MipsITB(MipsTLB): - type = 'ITB' + type = 'MipsITB' cxx_namespace = 'MipsISA' cxx_class = 'ITB' size = 64 class MipsUTB(MipsTLB): - type = 'UTB' + type = 'MipsUTB' cxx_namespace = 'MipsISA' cxx_class = 'UTB' size = 64 |