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author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
commit | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch) | |
tree | 4c212f665de2628eac6f84d389de7a79b6d0b933 /src/arch/mips/MipsTLB.py | |
parent | 08043c777f1f05f5e14581950013461f328965be (diff) | |
download | gem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/arch/mips/MipsTLB.py')
-rw-r--r-- | src/arch/mips/MipsTLB.py | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py index 41d46c572..16cbe6879 100644 --- a/src/arch/mips/MipsTLB.py +++ b/src/arch/mips/MipsTLB.py @@ -36,21 +36,5 @@ from BaseTLB import BaseTLB class MipsTLB(BaseTLB): type = 'MipsTLB' - abstract = True - size = Param.Int("TLB size") - -class MipsDTB(MipsTLB): - type = 'MipsDTB' - cxx_class = 'MipsISA::DTB' - size = 64 - -class MipsITB(MipsTLB): - type = 'MipsITB' - cxx_class = 'MipsISA::ITB' - size = 64 - -class MipsUTB(MipsTLB): - type = 'MipsUTB' - cxx_class = 'MipsISA::UTB' - size = 64 - + cxx_class = 'MipsISA::TLB' + size = Param.Int(64, "TLB size") |