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authorGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-26 20:24:18 -0700
commit537239b278f7b8171d2eb09ef7f99c332266c48f (patch)
tree31984b63cc542f0a57ca96262477575ab0130c09 /src/arch/mips/MipsTLB.py
parentf738afb865cd82487d6300259d6e87fb50660d2a (diff)
downloadgem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/arch/mips/MipsTLB.py')
-rw-r--r--src/arch/mips/MipsTLB.py20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
new file mode 100644
index 000000000..8c1a00abe
--- /dev/null
+++ b/src/arch/mips/MipsTLB.py
@@ -0,0 +1,20 @@
+from m5.SimObject import SimObject
+from m5.params import *
+class MipsTLB(SimObject):
+ type = 'MipsTLB'
+ abstract = True
+ #size = Param.Int("TLB size")
+
+class MipsDTB(MipsTLB):
+ type = 'MipsDTB'
+ cxx_namespace = 'MipsISA'
+ cxx_class = 'DTB'
+
+ #size = 64
+
+class MipsITB(MipsTLB):
+ type = 'MipsITB'
+ cxx_namespace = 'MipsISA'
+ cxx_class = 'ITB'
+
+ #size = 64