Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

1 files changed, 13 insertions, 6 deletions

diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index f4be39eca..1b746d8b0 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2004-2005 The Regents of The University of Michigan
+# Copyright (c) 2007 MIPS Technologies, Inc.
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -33,24 +33,31 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'mips':
-    Source('dsp.cc')
     Source('faults.cc')
     Source('regfile/int_regfile.cc')
+    Source('regfile/float_regfile.cc')
     Source('regfile/misc_regfile.cc')
     Source('regfile/regfile.cc')
     Source('tlb.cc')
+    Source('pagetable.cc')
     Source('utility.cc')
+    Source('dsp.cc')
 
     SimObject('MipsTLB.py')
-
     TraceFlag('MipsPRA')
 
     if env['FULL_SYSTEM']:
-        #Insert Full-System Files Here
-        pass
+	SimObject('MipsSystem.py')
+        Source('idle_event.cc')
+        Source('mips_core_specific.cc')
+        Source('vtophys.cc')
+        Source('system.cc')
+        Source('stacktrace.cc')
+        Source('linux/system.cc')
+	Source('interrupts.cc')
+        Source('bare_iron/system.cc')
     else:
         Source('process.cc')
-
         Source('linux/linux.cc')
         Source('linux/process.cc')