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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-30 18:39:38 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-30 18:39:38 -0700 |
| commit | 248033f31ea7198ab1339631cc198bb13935c2e8 (patch) | |
| tree | b7ee90ef322e3f65351eb1c39518553b4691e750 /src/arch/mips/SConscript | |
| parent | 8009b53c41b4b8643bc335ce293c6ba305b70608 (diff) | |
| download | gem5-248033f31ea7198ab1339631cc198bb13935c2e8.tar.xz | |
SE/FS: Get rid of FULL_SYSTEM in MIPS.
Diffstat (limited to 'src/arch/mips/SConscript')
| -rw-r--r-- | src/arch/mips/SConscript | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 282845f0d..7e2d4b806 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -33,32 +33,29 @@ Import('*') if env['TARGET_ISA'] == 'mips': + Source('bare_iron/system.cc') Source('dsp.cc') Source('faults.cc') + Source('idle_event.cc') Source('interrupts.cc') Source('isa.cc') + Source('linux/linux.cc') + Source('linux/process.cc') + Source('linux/system.cc') Source('pagetable.cc') + Source('process.cc') Source('remote_gdb.cc') + Source('stacktrace.cc') + Source('system.cc') Source('tlb.cc') Source('utility.cc') Source('vtophys.cc') SimObject('MipsInterrupts.py') - DebugFlag('MipsPRA') + SimObject('MipsSystem.py') SimObject('MipsTLB.py') - if env['FULL_SYSTEM']: - SimObject('MipsSystem.py') - Source('idle_event.cc') - Source('mips_core_specific.cc') - Source('system.cc') - Source('stacktrace.cc') - Source('linux/system.cc') - Source('bare_iron/system.cc') - else: - Source('process.cc') - Source('linux/linux.cc') - Source('linux/process.cc') + DebugFlag('MipsPRA') # Add in files generated by the ISA description. isa_desc_files = env.ISADesc('isa/main.isa') |