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authorGabe Black <gblack@eecs.umich.edu>2010-12-20 16:24:40 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-12-20 16:24:40 -0500
commit672d6a4b98165952e0afa0057f851f150bc657ec (patch)
tree4bd03e87c875477d172910ee1a0a838111949d83 /src/arch/mips/SConscript
parent89850d6370b29272788cb73165341ced68e3bd53 (diff)
downloadgem5-672d6a4b98165952e0afa0057f851f150bc657ec.tar.xz
Style: Replace some tabs with spaces.
Diffstat (limited to 'src/arch/mips/SConscript')
-rw-r--r--src/arch/mips/SConscript6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index ffc1f18eb..9e0275de7 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -44,15 +44,15 @@ if env['TARGET_ISA'] == 'mips':
TraceFlag('MipsPRA')
if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
- SimObject('MipsInterrupts.py')
+ SimObject('MipsSystem.py')
+ SimObject('MipsInterrupts.py')
Source('idle_event.cc')
Source('mips_core_specific.cc')
Source('vtophys.cc')
Source('system.cc')
Source('stacktrace.cc')
Source('linux/system.cc')
- Source('interrupts.cc')
+ Source('interrupts.cc')
Source('bare_iron/system.cc')
else:
Source('process.cc')