Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

1 files changed, 65 insertions, 0 deletions

diff --git a/src/arch/mips/bare_iron/system.cc b/src/arch/mips/bare_iron/system.cc
new file mode 100755
index 000000000..045db0dee
--- /dev/null
+++ b/src/arch/mips/bare_iron/system.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ *
+ * This software is part of the M5 simulator.
+ *
+ * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+ * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+ * TO THESE TERMS AND CONDITIONS.
+ *
+ * Permission is granted to use, copy, create derivative works and
+ * distribute this software and such derivative works for any purpose,
+ * so long as (1) the copyright notice above, this grant of permission,
+ * and the disclaimer below appear in all copies and derivative works
+ * made, (2) the copyright notice above is augmented as appropriate to
+ * reflect the addition of any new copyrightable work in a derivative
+ * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
+ * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
+ * advertising or publicity pertaining to the use or distribution of
+ * this software without specific, written prior authorization.
+ *
+ * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
+ * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+ * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+ * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+ * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+ * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+ * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+ * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+ * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+ * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+ * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ *
+ * Authors: Jaidev Patwardhan
+ *
+ */
+
+#include "arch/vtophys.hh"
+#include "arch/mips/bare_iron/system.hh"
+#include "arch/mips/system.hh"
+#include "cpu/thread_context.hh"
+#include "cpu/base.hh"
+#include "dev/platform.hh"
+#include "mem/physical.hh"
+#include "mem/port.hh"
+#include "params/BareIronMipsSystem.hh"
+#include "sim/byteswap.hh"
+
+using namespace std;
+using namespace MipsISA;
+
+
+BareIronMipsSystem::BareIronMipsSystem(Params *p)
+    : MipsSystem(p)
+{ }
+
+BareIronMipsSystem::~BareIronMipsSystem()
+{ }
+
+BareIronMipsSystem *
+BareIronMipsSystemParams::create()
+{
+    return new BareIronMipsSystem(this);
+}
+