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| author | Deyuan Guo <guodeyuan@tsinghua.org.cn> | 2012-01-12 09:59:00 -0500 |
|---|---|---|
| committer | Deyuan Guo <guodeyuan@tsinghua.org.cn> | 2012-01-12 09:59:00 -0500 |
| commit | 31b6941a52f859cf11c3f35ec4c0ac2f2f11eb14 (patch) | |
| tree | e22fe455ea5ef3751ed7bfcd09fd7ec3808170ff /src/arch/mips/faults.cc | |
| parent | a40ec5671fa023ad09de902028bd9e9ca1f1d7da (diff) | |
| download | gem5-31b6941a52f859cf11c3f35ec4c0ac2f2f11eb14.tar.xz | |
mips: Fix bugs in faults.cc/hh and tlb.cc for MIPS_FS
Diffstat (limited to 'src/arch/mips/faults.cc')
| -rw-r--r-- | src/arch/mips/faults.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 9ec93f3fe..00471aece 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -29,6 +29,8 @@ * Authors: Gabe Black * Korey Sewell * Jaidev Patwardhan + * Zhengxing Li + * Deyuan Guo */ #include "arch/mips/faults.hh" @@ -121,7 +123,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode) DPRINTF(MipsPRA, "PC: %s\n", pc); bool delay_slot = pc.pc() + sizeof(MachInst) != pc.npc(); tc->setMiscRegNoEffect(MISCREG_EPC, - pc.pc() - delay_slot ? sizeof(MachInst) : 0); + pc.pc() - (delay_slot ? sizeof(MachInst) : 0)); // Set Cause_EXCCODE field CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); |