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authorGabe Black <gblack@eecs.umich.edu>2011-09-19 06:17:20 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-09-19 06:17:20 -0700
commit59d7fc6b26f2cbbed09476499f04a25f886da984 (patch)
treeca704376c8fd55a3631f91ef704059b87b8b01f9 /src/arch/mips/faults.cc
parent717d4ae930a64226d909e97fc672dccfa6a19ca2 (diff)
downloadgem5-59d7fc6b26f2cbbed09476499f04a25f886da984.tar.xz
MIPS: Consolidate the two AddressErrorFault variants.
Diffstat (limited to 'src/arch/mips/faults.cc')
-rw-r--r--src/arch/mips/faults.cc21
1 files changed, 2 insertions, 19 deletions
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 464c2fe9e..038b73883 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -61,9 +61,6 @@ template <> FaultVals MipsFault<ResetFault>::vals =
template <> FaultVals MipsFault<AddressErrorFault>::vals =
{ "Address Error", 0x0180 };
-template <> FaultVals MipsFault<StoreAddressErrorFault>::vals =
- { "Store Address Error", 0x0180 };
-
template <> FaultVals MipsFault<SystemCallFault>::vals =
{ "Syscall", 0x0180 };
@@ -177,20 +174,6 @@ IntegerOverflowFault::invoke(ThreadContext *tc, StaticInstPtr inst)
}
void
-StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
-{
- DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x5);
- tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
-
- // Set new PC
- Addr HandlerBase;
- // Offset 0x180 - General Exception Vector
- HandlerBase = vect() + tc->readMiscReg(MISCREG_EBASE);
- setHandlerPC(HandlerBase, tc);
-}
-
-void
TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -244,8 +227,8 @@ void
AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
DPRINTF(MipsPRA, "%s encountered.\n", name());
- setExceptionState(tc, 0x4);
- tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
+ setExceptionState(tc, store ? 0x5 : 0x4);
+ tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
// Set new PC
Addr HandlerBase;