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authorGabe Black <gblack@eecs.umich.edu>2011-09-30 00:27:16 -0700
committerGabe Black <gblack@eecs.umich.edu>2011-09-30 00:27:16 -0700
commit35e20c7470a16cbc1187553375269800b980eb78 (patch)
tree7f2d469e98517c813f14e896e673f966f33b5fb5 /src/arch/mips/faults.hh
parent4fcf8e9959e281259a4e9e29fbd34e67fa6072dc (diff)
downloadgem5-35e20c7470a16cbc1187553375269800b980eb78.tar.xz
SE/FS: Use the new FullSystem constant where possible.
Diffstat (limited to 'src/arch/mips/faults.hh')
-rw-r--r--src/arch/mips/faults.hh7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 89b6924c6..bce828ec1 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -38,6 +38,7 @@
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
namespace MipsISA
{
@@ -163,7 +164,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
- if (FULL_SYSTEM) {
+ if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
tc->setMiscReg(MISCREG_CAUSE, cause);
@@ -197,7 +198,7 @@ class AddressFault : public MipsFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
- if (FULL_SYSTEM)
+ if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
}
};
@@ -249,7 +250,7 @@ class TlbFault : public AddressFault<T>
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code());