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| author | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2012-01-16 04:27:10 -0800 |
| commit | da2a4acc26ba264c3c4a12495776fd6a1c4fb133 (patch) | |
| tree | f142100388b9d1403492c97b0d323728ce18ef8a /src/arch/mips/faults.hh | |
| parent | 241cc0c8402f1b9f2ec20d1cc152d96930959b2a (diff) | |
| parent | a7394ad6807bd5e85f680184bf308673ca00534a (diff) | |
| download | gem5-da2a4acc26ba264c3c4a12495776fd6a1c4fb133.tar.xz | |
Merge yet again with the main repository.
Diffstat (limited to 'src/arch/mips/faults.hh')
| -rw-r--r-- | src/arch/mips/faults.hh | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh index bce828ec1..b90c38e99 100644 --- a/src/arch/mips/faults.hh +++ b/src/arch/mips/faults.hh @@ -29,6 +29,8 @@ * Authors: Gabe Black * Korey Sewell * Jaidev Patwardhan + * Zhengxing Li + * Deyuan Guo */ #ifndef __MIPS_FAULTS_HH__ @@ -88,7 +90,7 @@ class MipsFaultBase : public FaultBase virtual FaultVect base(ThreadContext *tc) const { StatusReg status = tc->readMiscReg(MISCREG_STATUS); - if (status.bev) + if (!status.bev) return tc->readMiscReg(MISCREG_EBASE); else return 0xbfc00200; @@ -167,7 +169,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault> if (FullSystem) { CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); cause.ce = coProcID; - tc->setMiscReg(MISCREG_CAUSE, cause); + tc->setMiscRegNoEffect(MISCREG_CAUSE, cause); } } }; @@ -179,7 +181,8 @@ class InterruptFault : public MipsFault<InterruptFault> offset(ThreadContext *tc) const { CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE); - return cause.iv ? 0x200 : 0x000; + // offset 0x200 for release 2, 0x180 for release 1. + return cause.iv ? 0x200 : 0x180; } }; @@ -251,9 +254,10 @@ class TlbFault : public AddressFault<T> StaticInstPtr inst = StaticInst::nullStaticInstPtr) { if (FullSystem) { - DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); - tc->pcState(this->vect(tc)); + DPRINTF(MipsPRA, "Fault %s encountered.\n", this->name()); + Addr vect = this->vect(tc); setTlbExceptionState(tc, this->code()); + tc->pcState(vect); } else { AddressFault<T>::invoke(tc, inst); } |