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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-15 13:39:44 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-15 13:39:44 -0400 |
| commit | 37aab4a1558b223e63cee1e5dd40195ddb7851c0 (patch) | |
| tree | 6d7a6b6b5e32497ffac7fd468afe8c19a77236ac /src/arch/mips/interrupts.cc | |
| parent | a45c9508ea3382f54d53f74bea48a61572343a4f (diff) | |
| download | gem5-37aab4a1558b223e63cee1e5dd40195ddb7851c0.tar.xz | |
sim: Don't clear the active CPU vector in System::initState
The system class currently clears the vector of active CPUs in
initState(). CPUs are added to the list by registerThreadContext()
which is called from BaseCPU::init(). This obviously breaks when the
System object is initialized after the CPUs. This changeset removes
the offending clear() call since the list will be empty after it has
been instantiated anyway.
Diffstat (limited to 'src/arch/mips/interrupts.cc')
0 files changed, 0 insertions, 0 deletions