summaryrefslogtreecommitdiff
path: root/src/arch/mips/interrupts.hh
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2009-07-21 01:09:05 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-21 01:09:05 -0700
commit74584d79b66b3459c72db6c74bfa9e22ee1ae23b (patch)
treef8a98156083103e9f883235e2fd91cccba76f179 /src/arch/mips/interrupts.hh
parent7548082d3baf578fe984c79f414dbefd96091359 (diff)
downloadgem5-74584d79b66b3459c72db6c74bfa9e22ee1ae23b.tar.xz
MIPS: Get MIPS_FS to compile, more style fixes.
Some breakage was from my BitUnion change, some was much older.
Diffstat (limited to 'src/arch/mips/interrupts.hh')
-rwxr-xr-xsrc/arch/mips/interrupts.hh25
1 files changed, 23 insertions, 2 deletions
diff --git a/src/arch/mips/interrupts.hh b/src/arch/mips/interrupts.hh
index 13d4f8512..c852bc9d0 100755
--- a/src/arch/mips/interrupts.hh
+++ b/src/arch/mips/interrupts.hh
@@ -31,20 +31,41 @@
#ifndef __ARCH_MIPS_INTERRUPT_HH__
#define __ARCH_MIPS_INTERRUPT_HH__
+#include <string>
+
#include "arch/mips/faults.hh"
#include "base/compiler.hh"
+#include "base/misc.hh"
+#include "params/MipsInterrupts.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_object.hh"
+
+class BaseCPU;
+class Checkpoint;
namespace MipsISA
{
-class Interrupts
+class Interrupts : public SimObject
{
public:
- Interrupts()
+ typedef MipsInterruptsParams Params;
+
+ const Params *
+ params() const
+ {
+ return dynamic_cast<const Params *>(_params);
+ }
+
+ Interrupts(Params * p) : SimObject(p)
{
newInfoSet = false;
}
+ void
+ setCPU(BaseCPU *_cpu)
+ {}
+
// post(int int_num, int index) is responsible
// for posting an interrupt. It sets a bit
// in intstatus corresponding to Cause IP*. The