arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.

1 files changed, 8 insertions, 3 deletions

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index a313b4382..3f4477132 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -39,20 +39,24 @@
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
 
 class BaseCPU;
 class Checkpoint;
 class EventManager;
+struct MipsISAParams;
 class ThreadContext;
 
 namespace MipsISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         // The MIPS name for this file is CP0 or Coprocessor 0
         typedef ISA CP0;
 
+        typedef MipsISAParams Params;
+
       protected:
         // Number of threads and vpes an individual ISA state can handle
         uint8_t numThreads;
@@ -69,8 +73,6 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
-        ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
-
         void clear();
 
         void configCP();
@@ -155,6 +157,9 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        const Params *params() const;
+
+        ISA(Params *p);
 
         int
         flattenIntIndex(int reg)