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authorAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-02-16 03:33:28 -0500
commitd0e1b8a19c6d58a49e5288938e9b12f3f10b9f51 (patch)
treef990864e7fb9ffaf11e3895e8337737941390aa2 /src/arch/mips/isa.hh
parent07ce60bdfa57eedf00f533704b5a2da3fa01b553 (diff)
downloadgem5-d0e1b8a19c6d58a49e5288938e9b12f3f10b9f51.tar.xz
arch: Make readMiscRegNoEffect const throughout
Finally took the plunge and made this apply to all ISAs, not just ARM.
Diffstat (limited to 'src/arch/mips/isa.hh')
-rw-r--r--src/arch/mips/isa.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index fea3f00ca..feb55e473 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -76,7 +76,7 @@ namespace MipsISA
void configCP();
- unsigned getVPENum(ThreadID tid);
+ unsigned getVPENum(ThreadID tid) const;
//////////////////////////////////////////////////////////
//
@@ -87,7 +87,7 @@ namespace MipsISA
//@TODO: MIPS MT's register view automatically connects
// Status to TCStatus depending on current thread
void updateCP0ReadView(int misc_reg, ThreadID tid) { }
- MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+ MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
//template <class TC>
MiscReg readMiscReg(int misc_reg,