arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

1 files changed, 5 insertions, 5 deletions

diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index 455ed70e7..c0f259666 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -53,7 +53,7 @@ output header {{
 
         /// Print a register name for disassembly given the unique
         /// dependence tag number (FP or int).
-        void printReg(std::ostream &os, int reg) const;
+        void printReg(std::ostream &os, RegId reg) const;
 
         std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
 
@@ -70,13 +70,13 @@ output header {{
 //Ouputs to decoder.cc
 output decoder {{
 
-    void MipsStaticInst::printReg(std::ostream &os, int reg) const
+    void MipsStaticInst::printReg(std::ostream &os, RegId reg) const
     {
-        if (reg < FP_Reg_Base) {
-            ccprintf(os, "r%d", reg);
+        if (reg.regClass == IntRegClass) {
+            ccprintf(os, "r%d", reg.regIdx);
         }
         else {
-            ccprintf(os, "f%d", reg - FP_Reg_Base);
+            ccprintf(os, "f%d", reg.regIdx);
         }
     }