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author | Korey Sewell <ksewell@umich.edu> | 2006-07-26 18:47:06 -0400 |
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committer | Korey Sewell <ksewell@umich.edu> | 2006-07-26 18:47:06 -0400 |
commit | 95561dc138243b1fda266ed4ef4ffdc64700c353 (patch) | |
tree | e08ac81c9d7db5930ef459ccaf4e3308a8d0f510 /src/arch/mips/isa/decoder.isa | |
parent | 36e9ca5611b3fb38cba2fc190836c022d99973e4 (diff) | |
download | gem5-95561dc138243b1fda266ed4ef4ffdc64700c353.tar.xz |
MIPS ISA runs 'hello world' in O3CPU ...
src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
Diffstat (limited to 'src/arch/mips/isa/decoder.isa')
-rw-r--r-- | src/arch/mips/isa/decoder.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 13f6f9712..d65e3eb94 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -133,7 +133,8 @@ decode OPCODE_HI default Unknown::unknown() { format BasicOp { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); - 0x4: syscall({{ xc->syscall(R2); }}, IsNonSpeculative); + 0x4: syscall({{ xc->syscall(R2); }}, + IsSerializeAfter, IsNonSpeculative); 0x7: sync({{ ; }}, IsMemBarrier); } |