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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-13 08:09:09 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-02-13 08:09:09 -0800 |
| commit | f55fd68f884d07c65ff78cd0b5a762dba61ce690 (patch) | |
| tree | 2c01ead62810f34e7324972c77ac03c1fcf786c8 /src/arch/mips/isa/decoder.isa | |
| parent | ca5cd68df4967b306625723c13eab9282c0f2372 (diff) | |
| download | gem5-f55fd68f884d07c65ff78cd0b5a762dba61ce690.tar.xz | |
Update MIPS ISA description to work with new write result interface
for store conditional.
--HG--
extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
Diffstat (limited to 'src/arch/mips/isa/decoder.isa')
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 99c9e1604..3a8688797 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -1093,6 +1093,9 @@ decode OPCODE_HI default Unknown::unknown() { 0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}}, {{ uint64_t tmp = write_result; Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw; + if (tmp == 1) { + xc->setStCondFailures(0); + } }}, mem_flags=LOCKED, inst_flags = IsStoreConditional); format StoreMemory { |