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| author | Gabe Black <gblack@eecs.umich.edu> | 2011-10-31 01:09:44 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-10-31 01:09:44 -0700 |
| commit | d735abe5dabf483aafb0ccfb0a70cb7c3b0a5a74 (patch) | |
| tree | dd273d4e65d4ba5a11a5928f3aa4d012fbcd2e19 /src/arch/mips/isa/decoder.isa | |
| parent | ce2f9625f4c4ed0bf6a79eede184a222e61b1f26 (diff) | |
| download | gem5-d735abe5dabf483aafb0ccfb0a70cb7c3b0a5a74.tar.xz | |
GCC: Get everything working with gcc 4.6.1.
And by "everything" I mean all the quick regressions.
Diffstat (limited to 'src/arch/mips/isa/decoder.isa')
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 7b8dafdba..179e409dd 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -497,8 +497,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + FP_Base_DepTag); - data = insertBits(data, top_bit, - bottom_bit, Rt); + data = insertBits(data, MT_H ? 63 : 31, + MT_H ? 32 : 0, Rt); xc->setRegOtherThread(RD + FP_Base_DepTag, data); }}); @@ -532,7 +532,7 @@ decode OPCODE_HI default Unknown::unknown() { panic("FP Control Value (%d) " "Not Available. Ignoring " "Access to Floating Control " - "Status Register", FS); + "S""tatus Register", FS); } xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); }}); @@ -776,7 +776,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Index & 0x7FFFFFFF, SP); }}); 0x06: tlbwr({{ @@ -842,7 +841,6 @@ decode OPCODE_HI default Unknown::unknown() { bits(pageGrain, pageGrain.esp) == 1) { SP = 1; } - IndexReg index = Index; Ptr->insertAt(newEntry, Random, SP); }}); |