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authorKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
committerKorey Sewell <ksewell@umich.edu>2007-11-13 16:58:16 -0500
commit269259004943b80916ec9b6354f2fc00c811c88b (patch)
tree4a01b0300aef6692a787f85d42280a1dbdb086e6 /src/arch/mips/isa/formats/control.isa
parent422ab8bec0034a6b703578ec2c92350c6382875a (diff)
downloadgem5-269259004943b80916ec9b6354f2fc00c811c88b.tar.xz
Add in files from merge-bare-iron, get them compiling in FS and SE mode
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
Diffstat (limited to 'src/arch/mips/isa/formats/control.isa')
-rw-r--r--src/arch/mips/isa/formats/control.isa189
1 files changed, 154 insertions, 35 deletions
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 1de2948be..4593aa52b 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -1,32 +1,39 @@
// -*- mode:c++ -*-
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
+// Copyright N) 2007 MIPS Technologies, Inc. All Rights Reserved
+
+// This software is part of the M5 simulator.
+
+// THIS IS A LEGAL AGREEMENT. BY DOWNLOADING, USING, COPYING, CREATING
+// DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+// TO THESE TERMS AND CONDITIONS.
+
+// Permission is granted to use, copy, create derivative works and
+// distribute this software and such derivative works for any purpose,
+// so long as (1) the copyright notice above, this grant of permission,
+// and the disclaimer below appear in all copies and derivative works
+// made, (2) the copyright notice above is augmented as appropriate to
+// reflect the addition of any new copyrightable work in a derivative
+// work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+// the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+// advertising or publicity pertaining to the use or distribution of
+// this software without specific, written prior authorization.
+
+// THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B MIPS MAKES NO WARRANTIES AND
+// DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+// OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+// NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+// IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+// INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+// ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+// THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+// IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+// STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+// POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
+// Jaidev Patwardhan
////////////////////////////////////////////////////////////////////
//
@@ -48,6 +55,19 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class CP0TLB : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ CP0TLB(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
class CP1Control : public MipsStaticInst
{
@@ -65,7 +85,7 @@ output header {{
}};
// Basic instruction class execute method template.
-def template ControlExecute {{
+def template CP0Execute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -75,7 +95,7 @@ def template ControlExecute {{
if (isCoprocessorEnabled(xc, 0)) {
%(code)s;
} else {
- fault = new CoprocessorUnusableFault();
+ fault = new CoprocessorUnusableFault(0);
}
if(fault == NoFault)
@@ -86,6 +106,57 @@ def template ControlExecute {{
}
}};
+def template CP1Execute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (isCoprocessorEnabled(xc, 1)) {
+ %(code)s;
+ } else {
+ fault = new CoprocessorUnusableFault(1);
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+// Basic instruction class execute method template.
+def template ControlTLBExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+#if FULL_SYSTEM
+ if (isCoprocessor0Enabled(xc)) {
+ if(isMMUTLB(xc)){
+ %(code)s;
+ } else {
+ fault = new ReservedInstructionFault();
+ }
+ } else {
+ fault = new CoprocessorUnusableFault(0);
+ }
+#else // Syscall Emulation Mode - No TLB Instructions
+ fault = new ReservedInstructionFault();
+#endif
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+
+ }
+}};
+
//Outputs to decoder.cc
output decoder {{
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
@@ -94,7 +165,12 @@ output decoder {{
ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
-
+ std::string CP0TLB::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+ ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
+ return ss.str();
+ }
std::string CP1Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@@ -107,29 +183,65 @@ output decoder {{
output exec {{
bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
+ MiscReg Stat = xc->readMiscReg(MipsISA::Status);
switch(cop_num)
{
case 0:
+ {
#if FULL_SYSTEM
- if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
- // Unable to use Status_CU0, etc directly, using bitfields & masks
+ MiscReg Dbg = xc->readMiscReg(MipsISA::Debug);
+ if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
+ && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+ && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
return false;
}
#else
//printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
#endif
+ }
break;
case 1:
+ if((Stat & 0x20000000) == 0) // CU1 is reset
+ return false;
break;
case 2:
+ if((Stat & 0x40000000) == 0) // CU2 is reset
+ return false;
break;
case 3:
+ if((Stat & 0x80000000) == 0) // CU3 is reset
+ return false;
break;
default: panic("Invalid Coprocessor Number Specified");
break;
}
return true;
}
+ bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status);
+ MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug);
+ if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible
+ && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible
+ && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
+ return false;
+ }
+#else
+ //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
+#endif
+ return true;
+ }
+ bool isMMUTLB(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80)
+ return true;
+#endif
+ return false;
+ }
}};
def format CP0Control(code, *flags) {{
@@ -138,16 +250,23 @@ def format CP0Control(code, *flags) {{
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = ControlExecute.subst(iop)
+ exec_output = CP0Execute.subst(iop)
+}};
+def format CP0TLB(code, *flags) {{
+ flags += ('IsNonSpeculative', )
+ iop = InstObjParams(name, Name, 'CP0Control', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ControlTLBExecute.subst(iop)
}};
-
def format CP1Control(code, *flags) {{
flags += ('IsNonSpeculative', )
iop = InstObjParams(name, Name, 'CP1Control', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = ControlExecute.subst(iop)
+ exec_output = CP1Execute.subst(iop)
}};