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author | Gabe Black <gabeblack@google.com> | 2017-11-02 01:58:38 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2017-11-02 09:43:35 +0000 |
commit | 8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch) | |
tree | f791cd8adccee52d054f5a10b62948021a3d121b /src/arch/mips/isa/formats/control.isa | |
parent | 97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff) | |
download | gem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz |
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/mips/isa/formats/control.isa')
-rw-r--r-- | src/arch/mips/isa/formats/control.isa | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index 123468287..00600712c 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -80,7 +80,8 @@ output header {{ // Basic instruction class execute method template. def template CP0Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -101,7 +102,8 @@ def template CP0Execute {{ }}; def template CP1Execute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -122,7 +124,8 @@ def template CP1Execute {{ }}; // Basic instruction class execute method template. def template ControlTLBExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, Trace::InstRecord *traceData) const + Fault %(class_name)s::execute( + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; %(op_decl)s; @@ -173,15 +176,15 @@ output decoder {{ }}; output header {{ - bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num); + bool isCoprocessorEnabled(ExecContext *xc, unsigned cop_num); - bool isMMUTLB(%(CPU_exec_context)s *xc); + bool isMMUTLB(ExecContext *xc); }}; output exec {{ bool - isCoprocessorEnabled(CPU_EXEC_CONTEXT *xc, unsigned cop_num) + isCoprocessorEnabled(ExecContext *xc, unsigned cop_num) { if (!FullSystem) return true; @@ -203,7 +206,7 @@ output exec {{ } bool inline - isCoprocessor0Enabled(CPU_EXEC_CONTEXT *xc) + isCoprocessor0Enabled(ExecContext *xc) { if (FullSystem) { MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); @@ -219,7 +222,7 @@ output exec {{ } bool - isMMUTLB(CPU_EXEC_CONTEXT *xc) + isMMUTLB(ExecContext *xc) { MiscReg Config = xc->readMiscReg(MISCREG_CONFIG); return FullSystem && (Config & 0x380) == 0x80; |