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| author | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-06-22 19:03:42 -0400 |
| commit | 753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch) | |
| tree | 9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/arch/mips/isa/formats/fp.isa | |
| parent | 16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff) | |
| download | gem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz | |
mips import pt. 1
src/arch/mips/SConscript:
"mips import pt.1".
--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/arch/mips/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index ac6805cc7..4b340e2e6 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -87,6 +87,12 @@ output decoder {{ }}; output exec {{ + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + //@TODO: Implement correct CP0 checks to see if the CP1 + // unit is enable or not + return NoFault; + } //If any operand is Nan return the appropriate QNaN template <class T> @@ -145,7 +151,7 @@ output exec {{ uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); + cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits)); if (traceData) { traceData->setData(mips_nan); } return true; @@ -160,6 +166,7 @@ output exec {{ //Read FCSR from FloatRegFile uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile |