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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-23 13:26:30 -0700 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-23 13:26:30 -0700 |
| commit | 245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe (patch) | |
| tree | 7ca0de263839f60d35cd6cf0ca8c17d94c375209 /src/arch/mips/isa/formats/fp.isa | |
| parent | 57ff2604e59647c6afe988767186f13c80c1aa16 (diff) | |
| parent | ac19e0c5050219cbb0579a319fa3fab5cf92835d (diff) | |
| download | gem5-245b0bd9b94bfaaa188b7e945f91c0e4a9909cbe.tar.xz | |
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
src/base/traceflags.py:
Hand merge.
--HG--
extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924
Diffstat (limited to 'src/arch/mips/isa/formats/fp.isa')
| -rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index ac6805cc7..4b340e2e6 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -87,6 +87,12 @@ output decoder {{ }}; output exec {{ + inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) + { + //@TODO: Implement correct CP0 checks to see if the CP1 + // unit is enable or not + return NoFault; + } //If any operand is Nan return the appropriate QNaN template <class T> @@ -145,7 +151,7 @@ output exec {{ uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits)); + cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits)); if (traceData) { traceData->setData(mips_nan); } return true; @@ -160,6 +166,7 @@ output exec {{ //Read FCSR from FloatRegFile uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile |