diff options
author | Gabe Black <gabeblack@google.com> | 2017-11-02 01:58:38 -0700 |
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committer | Gabe Black <gabeblack@google.com> | 2017-11-02 09:43:35 +0000 |
commit | 8be75f49fd37712e7cf04c0853bb7504f69a04d6 (patch) | |
tree | f791cd8adccee52d054f5a10b62948021a3d121b /src/arch/mips/isa/formats/mem.isa | |
parent | 97c68e8fc56baa39ce7901ac1f73d2ff79b550f2 (diff) | |
download | gem5-8be75f49fd37712e7cf04c0853bb7504f69a04d6.tar.xz |
alpha,arm,mips,power,riscv,sparc,x86,isa: De-specialize ExecContexts.
The ISA parser used to generate different copies of exec functions
for each exec context class a particular CPU wanted to use. That's
since been changed so that those functions take a pointer to the base
ExecContext, so the code which would generate those extra functions
can be removed, and some functions which used to be templated on an
ExecContext subclass can be untemplated, or minimally less templated.
Now that some functions aren't going to be instantiated multiple times
with different signatures, there are also opportunities to collapse
templates and make many instruction definitions simpler within the
parser. Since those changes will be less mechanical, they're left for
later changes and will probably be done in smaller increments.
Change-Id: I0015307bb02dfb9c60380b56d2a820f12169ebea
Reviewed-on: https://gem5-review.googlesource.com/5381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/mips/isa/formats/mem.isa')
-rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 39 |
1 files changed, 18 insertions, 21 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 052ead82c..9e5f538e6 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -97,7 +97,7 @@ output decoder {{ }}; output header {{ - uint64_t getMemData(%(CPU_exec_context)s *xc, Packet *packet); + uint64_t getMemData(ExecContext *xc, Packet *packet); }}; @@ -105,7 +105,7 @@ output exec {{ /** return data in cases where there the size of data is only known in the packet */ - uint64_t getMemData(CPU_EXEC_CONTEXT *xc, Packet *packet) { + uint64_t getMemData(ExecContext *xc, Packet *packet) { switch (packet->getSize()) { case 1: @@ -153,16 +153,16 @@ def template LoadStoreDeclare {{ }}; def template EACompDeclare {{ - Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault eaComp(ExecContext *, Trace::InstRecord *) const; }}; def template InitiateAccDeclare {{ - Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; }}; def template CompleteAccDeclare {{ - Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const; + Fault completeAcc(Packet *, ExecContext *, Trace::InstRecord *) const; }}; def template LoadStoreConstructor {{ @@ -176,8 +176,7 @@ def template LoadStoreConstructor {{ def template EACompExecute {{ Fault - %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc, - Trace::InstRecord *traceData) const + %(class_name)s::eaComp(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; Fault fault = NoFault; @@ -203,7 +202,7 @@ def template EACompExecute {{ }}; def template LoadExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -235,7 +234,7 @@ def template LoadExecute {{ def template LoadInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -261,8 +260,7 @@ def template LoadInitiateAcc {{ }}; def template LoadCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -292,7 +290,7 @@ def template LoadCompleteAcc {{ }}; def template StoreExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -326,7 +324,7 @@ def template StoreExecute {{ def template StoreFPExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -361,7 +359,7 @@ def template StoreFPExecute {{ }}; def template StoreCondExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -395,7 +393,7 @@ def template StoreCondExecute {{ }}; def template StoreInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA; @@ -422,7 +420,7 @@ def template StoreInitiateAcc {{ def template StoreCompleteAcc {{ Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + ExecContext *xc, Trace::InstRecord *traceData) const { return NoFault; @@ -431,7 +429,7 @@ def template StoreCompleteAcc {{ def template StoreCondCompleteAcc {{ Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + ExecContext *xc, Trace::InstRecord *traceData) const { Fault fault = NoFault; @@ -454,7 +452,7 @@ def template StoreCondCompleteAcc {{ }}; def template MiscExecute {{ - Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const { Addr EA M5_VAR_USED = 0; @@ -474,7 +472,7 @@ def template MiscExecute {{ }}; def template MiscInitiateAcc {{ - Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const { panic("Misc instruction does not support split access method!"); @@ -484,8 +482,7 @@ def template MiscInitiateAcc {{ def template MiscCompleteAcc {{ - Fault %(class_name)s::completeAcc(Packet *pkt, - CPU_EXEC_CONTEXT *xc, + Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc, Trace::InstRecord *traceData) const { panic("Misc instruction does not support split access method!"); |