Add in files from merge-bare-iron, get them compiling in FS and SE mode

--HG--
extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251

1 files changed, 167 insertions, 28 deletions

diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 03068fa74..bf91e1fae 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -1,33 +1,39 @@
 // -*- mode:c++ -*-
 
+// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+
+//  This software is part of the M5 simulator.
+
+//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
+//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
+//  TO THESE TERMS AND CONDITIONS.
+
+//  Permission is granted to use, copy, create derivative works and
+//  distribute this software and such derivative works for any purpose,
+//  so long as (1) the copyright notice above, this grant of permission,
+//  and the disclaimer below appear in all copies and derivative works
+//  made, (2) the copyright notice above is augmented as appropriate to
+//  reflect the addition of any new copyrightable work in a derivative
+//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
+//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
+//  advertising or publicity pertaining to the use or distribution of
+//  this software without specific, written prior authorization.
+
+//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
+//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
+//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
+//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
+//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
+//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
+//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
+//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
+//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
+//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
+//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+
+//Authors: Korey L. Sewell
 
-// Copyright (c) 2006 The Regents of The University of Michigan
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are
-// met: redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer;
-// redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution;
-// neither the name of the copyright holders nor the names of its
-// contributors may be used to endorse or promote products derived from
-// this software without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -59,6 +65,57 @@ output header {{
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
     };
+    class CP0Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP0Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+    class CP1Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP1Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
+    class CP2Unimplemented : public MipsStaticInst
+    {
+      public:
+        /// Constructor
+        CP2Unimplemented(const char *_mnemonic, MachInst _machInst)
+            : MipsStaticInst(_mnemonic, _machInst, No_OpClass)
+        {
+            // don't call execute() (which panics) if we're on a
+            // speculative path
+            flags[IsNonSpeculative] = true;
+        }
+
+        %(BasicExecDeclare)s
+
+        std::string
+        generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 
     /**
      * Base class for unimplemented instructions that cause a warning
@@ -101,6 +158,26 @@ output decoder {{
     }
 
     std::string
+    CP0Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
+    std::string
+    CP1Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+    std::string
+    CP2Unimplemented::generateDisassembly(Addr pc,
+                                           const SymbolTable *symtab) const
+    {
+        return csprintf("%-10s (unimplemented)", mnemonic);
+    }
+
+    std::string
     WarnUnimplemented::generateDisassembly(Addr pc,
                                            const SymbolTable *symtab) const
     {
@@ -120,6 +197,56 @@ output exec {{
     }
 
     Fault
+    CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 0)) {
+        return new CoprocessorUnusableFault(0);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+
+    Fault
+    CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 1)) {
+        return new CoprocessorUnusableFault(1);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+    Fault
+    CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
+                               Trace::InstRecord *traceData) const
+    {
+#if  FULL_SYSTEM
+      if (!isCoprocessorEnabled(xc, 2)) {
+        return new CoprocessorUnusableFault(2);
+      }
+      return new ReservedInstructionFault;
+#else
+        panic("attempt to execute unimplemented instruction '%s' "
+              "(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
+              inst2string(machInst));
+        return new UnimplementedOpcodeFault;
+#endif
+    }
+
+    Fault
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
@@ -136,8 +263,20 @@ output exec {{
 def format FailUnimpl() {{
     iop = InstObjParams(name, 'FailUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)
-}};
 
+}};
+def format CP0Unimpl() {{
+    iop = InstObjParams(name, 'CP0Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP1Unimpl() {{
+    iop = InstObjParams(name, 'CP1Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
+def format CP2Unimpl() {{
+    iop = InstObjParams(name, 'CP2Unimplemented')
+    decode_block = BasicDecodeWithMnemonic.subst(iop)
+}};
 def format WarnUnimpl() {{
     iop = InstObjParams(name, 'WarnUnimplemented')
     decode_block = BasicDecodeWithMnemonic.subst(iop)