summaryrefslogtreecommitdiff
path: root/src/arch/mips/isa/formats/util.isa
diff options
context:
space:
mode:
authorKorey Sewell <ksewell@umich.edu>2010-03-27 02:23:00 -0400
committerKorey Sewell <ksewell@umich.edu>2010-03-27 02:23:00 -0400
commit1c98bc5a567599f9fdc7d9940dbfe907091cb3b4 (patch)
tree9b9b7b9c049fdc4d34758cf1e62b9f3e33129586 /src/arch/mips/isa/formats/util.isa
parent941399728fa387bd472041c01b6913e5b3e64909 (diff)
parent6b293c73fd19b73758547e1bfbe38a23d1800747 (diff)
downloadgem5-1c98bc5a567599f9fdc7d9940dbfe907091cb3b4.tar.xz
m5: merge inorder updates
Diffstat (limited to 'src/arch/mips/isa/formats/util.isa')
-rw-r--r--src/arch/mips/isa/formats/util.isa3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index a6edffeda..708338074 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -38,9 +38,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # add hook to get effective addresses into execution trace output.
- ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
-
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need