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authorKorey Sewell <ksewell@umich.edu>2006-06-09 17:07:13 -0400
committerKorey Sewell <ksewell@umich.edu>2006-06-09 17:07:13 -0400
commit4cc31e1aefc337fe37c4b6373fe263e8b26e0b7d (patch)
tree79030095be1a846e433bf9de7d31db8135811382 /src/arch/mips/isa/formats
parent68e470f78aac9fc5ea15f0840deda0972bef7666 (diff)
downloadgem5-4cc31e1aefc337fe37c4b6373fe263e8b26e0b7d.tar.xz
add fcntl64Func
use ThreadContext rename src/arch/mips/isa/formats/branch.isa: src/arch/mips/isa/formats/fp.isa: src/arch/mips/isa/includes.isa: Use ThreadContext src/sim/syscall_emul.cc: fcntl64 function using TC src/sim/syscall_emul.hh: Add fcntl64func --HG-- extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
Diffstat (limited to 'src/arch/mips/isa/formats')
-rw-r--r--src/arch/mips/isa/formats/branch.isa8
-rw-r--r--src/arch/mips/isa/formats/fp.isa14
2 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index 6f8cebed0..e8843da03 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -88,7 +88,7 @@ output header {{
{
}
- Addr branchTarget(ExecContext *xc) const;
+ Addr branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -103,10 +103,10 @@ output decoder {{
}
Addr
- Jump::branchTarget(ExecContext *xc) const
+ Jump::branchTarget(ThreadContext *tc) const
{
- Addr NPC = xc->readPC() + 4;
- uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+ Addr NPC = tc->readPC() + 4;
+ uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 6647f9361..1803c0e73 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -95,7 +95,7 @@ output exec {{
template <class T>
bool
- fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *xc, const T dest_val,
+ fpInvalidOp(FPOp *inst, %(CPU_exec_context)s *cpu, const T dest_val,
Trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
@@ -111,13 +111,13 @@ output exec {{
}
//Set value to QNAN
- xc->setFloatRegBits(inst, 0, mips_nan, size);
+ cpu->setFloatRegBits(inst, 0, mips_nan, size);
//Read FCSR from FloatRegFile
- uint32_t fcsr_bits = xc->cpuXC->readFloatRegBits(FCSR);
+ uint32_t fcsr_bits = cpu->tc->readFloatRegBits(FCSR);
//Write FCSR from FloatRegFile
- xc->cpuXC->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+ cpu->tc->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
if (traceData) { traceData->setData(mips_nan); }
return true;
@@ -127,15 +127,15 @@ output exec {{
}
void
- fpResetCauseBits(%(CPU_exec_context)s *xc)
+ fpResetCauseBits(%(CPU_exec_context)s *cpu)
{
//Read FCSR from FloatRegFile
- uint32_t fcsr = xc->cpuXC->readFloatRegBits(FCSR);
+ uint32_t fcsr = cpu->tc->readFloatRegBits(FCSR);
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
//Write FCSR from FloatRegFile
- xc->cpuXC->setFloatRegBits(FCSR, fcsr);
+ cpu->tc->setFloatRegBits(FCSR, fcsr);
}
}};