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authorKorey Sewell <ksewell@umich.edu>2007-06-22 19:03:42 -0400
committerKorey Sewell <ksewell@umich.edu>2007-06-22 19:03:42 -0400
commit753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch)
tree9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/arch/mips/isa/formats
parent16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff)
downloadgem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz
mips import pt. 1
src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/arch/mips/isa/formats')
-rw-r--r--src/arch/mips/isa/formats/branch.isa54
-rw-r--r--src/arch/mips/isa/formats/control.isa127
-rwxr-xr-xsrc/arch/mips/isa/formats/dsp.isa218
-rw-r--r--src/arch/mips/isa/formats/formats.isa3
-rw-r--r--src/arch/mips/isa/formats/fp.isa9
-rw-r--r--src/arch/mips/isa/formats/int.isa159
-rw-r--r--src/arch/mips/isa/formats/mem.isa117
-rw-r--r--src/arch/mips/isa/formats/mt.isa173
-rw-r--r--src/arch/mips/isa/formats/tlbop.isa4
-rw-r--r--src/arch/mips/isa/formats/util.isa40
10 files changed, 723 insertions, 181 deletions
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index a67f04dca..e959e4c1b 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -36,6 +36,7 @@
output header {{
#include <iostream>
+ using namespace std;
/**
* Base class for instructions whose disassembly is not purely a
@@ -216,7 +217,7 @@ output decoder {{
}
}};
-def format Branch(code,*opt_flags) {{
+def format Branch(code, *opt_flags) {{
not_taken_code = ' NNPC = NNPC;\n'
not_taken_code += '} \n'
@@ -230,13 +231,13 @@ def format Branch(code,*opt_flags) {{
not_taken_code = ' NPC = NNPC;\n'
not_taken_code += ' NNPC = NNPC + 4;\n'
not_taken_code += '} \n'
- inst_flags = ('IsCondDelaySlot', )
+ inst_flags += ('IsCondDelaySlot', )
else:
inst_flags += (x, )
#Take into account uncond. branch instruction
- if 'cond == 1' in code:
- inst_flags += ('IsUnCondControl', )
+ if 'cond = 1' in code:
+ inst_flags += ('IsUncondControl', )
else:
inst_flags += ('IsCondControl', )
@@ -254,6 +255,51 @@ def format Branch(code,*opt_flags) {{
exec_output = BasicExecute.subst(iop)
}};
+def format DspBranch(code, *opt_flags) {{
+ not_taken_code = ' NNPC = NNPC;\n'
+ not_taken_code += '} \n'
+
+ #Build Instruction Flags
+ #Use Link & Likely Flags to Add Link/Condition Code
+ inst_flags = ('IsDirectControl', )
+ for x in opt_flags:
+ if x == 'Link':
+ code += 'R31 = NNPC;\n'
+ elif x == 'Likely':
+ not_taken_code = ' NPC = NNPC;\n'
+ not_taken_code += ' NNPC = NNPC + 4;\n'
+ not_taken_code += '} \n'
+ inst_flags += ('IsCondDelaySlot', )
+ else:
+ inst_flags += (x, )
+
+ #Take into account uncond. branch instruction
+ if 'cond = 1' in code:
+ inst_flags += ('IsUncondControl', )
+ else:
+ inst_flags += ('IsCondControl', )
+
+ #Declaration code
+ decl_code = 'bool cond;\n'
+ decl_code += 'uint32_t dspctl;\n'
+
+ #Fetch code
+ fetch_code = 'dspctl = DSPControl;\n'
+
+ #Condition code
+ code = decl_code + fetch_code + code
+ code += 'if (cond) {\n'
+ code += ' NNPC = NPC + disp;\n'
+ code += '} else {\n'
+ code += not_taken_code
+
+ iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = BasicExecute.subst(iop)
+}};
+
def format Jump(code, *opt_flags) {{
#Build Instruction Flags
#Use Link Flag to Add Link Code
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 1c63a6e22..1de2948be 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -30,45 +30,32 @@
////////////////////////////////////////////////////////////////////
//
-// Integer operate instructions
+// Coprocessor instructions
//
//Outputs to decoder.hh
output header {{
- class Control : public MipsStaticInst
- {
- protected:
-
- /// Constructor
- Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass)
- {
- }
-
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-
- class CP0Control : public Control
+ class CP0Control : public MipsStaticInst
{
protected:
/// Constructor
CP0Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
- Control(mnem, _machInst, __opClass)
+ MipsStaticInst(mnem, _machInst, __opClass)
{
}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
- class CP1Control : public Control
+ class CP1Control : public MipsStaticInst
{
protected:
/// Constructor
CP1Control(const char *mnem, MachInst _machInst, OpClass __opClass) :
- Control(mnem, _machInst, __opClass)
+ MipsStaticInst(mnem, _machInst, __opClass)
{
}
@@ -77,46 +64,34 @@ output header {{
}};
-//Outputs to decoder.cc
-output decoder {{
- std::string Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+// Basic instruction class execute method template.
+def template ControlExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
- std::stringstream ss;
-
- ccprintf(ss, "%-10s ", mnemonic);
-
- if (mnemonic == "mfc0" || mnemonic == "mtc0") {
- ccprintf(ss, "%-10s %d,%d,%d", mnemonic,RT,RD,SEL);
- } else {
-
- // just print the first dest... if there's a second one,
- // it's generally implicit
- if (_numDestRegs > 0) {
- printReg(ss, _destRegIdx[0]);
- }
-
- ss << ", ";
-
- // just print the first two source regs... if there's
- // a third one, it's a read-modify-write dest (Rc),
- // e.g. for CMOVxx
- if (_numSrcRegs > 0) {
- printReg(ss, _srcRegIdx[0]);
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ if (isCoprocessorEnabled(xc, 0)) {
+ %(code)s;
+ } else {
+ fault = new CoprocessorUnusableFault();
}
- if (_numSrcRegs > 1) {
- ss << ", ";
- printReg(ss, _srcRegIdx[1]);
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
}
- }
-
- return ss.str();
+ return fault;
}
+}};
+//Outputs to decoder.cc
+output decoder {{
std::string CP0Control::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
- ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
+ ccprintf(ss, "%-10s r%d, %d, %d", mnemonic, RT, RD, SEL);
return ss.str();
}
@@ -129,28 +104,50 @@ output decoder {{
}};
-def format System(code, *flags) {{
- iop = InstObjParams(name, Name, 'Control', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+output exec {{
+ bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
+ {
+ switch(cop_num)
+ {
+ case 0:
+#if FULL_SYSTEM
+ if((xc->readMiscReg(MipsISA::Status) & 0x10000006) == 0 && (xc->readMiscReg(MipsISA::Debug) & 0x40000000 ) == 0) {
+ // Unable to use Status_CU0, etc directly, using bitfields & masks
+ return false;
+ }
+#else
+ //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n");
+#endif
+ break;
+ case 1:
+ break;
+ case 2:
+ break;
+ case 3:
+ break;
+ default: panic("Invalid Coprocessor Number Specified");
+ break;
+ }
+ return true;
+ }
}};
def format CP0Control(code, *flags) {{
- iop = InstObjParams(name, Name, 'CP0Control', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ flags += ('IsNonSpeculative', )
+ iop = InstObjParams(name, Name, 'CP0Control', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ControlExecute.subst(iop)
}};
def format CP1Control(code, *flags) {{
- iop = InstObjParams(name, Name, 'CP1Control', code, flags)
- header_output = BasicDeclare.subst(iop)
- decoder_output = BasicConstructor.subst(iop)
- decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ flags += ('IsNonSpeculative', )
+ iop = InstObjParams(name, Name, 'CP1Control', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ControlExecute.subst(iop)
}};
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
new file mode 100755
index 000000000..768f3dd7d
--- /dev/null
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -0,0 +1,218 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+
+////////////////////////////////////////////////////////////////////
+//
+// DSP integer operate instructions
+//
+output header {{
+#include <iostream>
+ using namespace std;
+ /**
+ * Base class for integer operations.
+ */
+ class DspIntOp : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ DspIntOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+ };
+
+ class DspHiLoOp : public MipsStaticInst
+ {
+ protected:
+
+ /// Constructor
+ DspHiLoOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass)
+ {
+ }
+ };
+}};
+
+// Dsp instruction class execute method template.
+def template DspExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (isDspPresent(xc))
+ {
+ if (isDspEnabled(xc))
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+ else
+ {
+ fault = new DspStateDisabledFault();
+ }
+ }
+ else
+ {
+ fault = new ReservedInstructionFault();
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// DspHiLo instruction class execute method template.
+def template DspHiLoExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if (isDspPresent(xc))
+ {
+ if (isDspEnabled(xc))
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+ else
+ {
+ fault = new DspStateDisabledFault();
+ }
+ }
+ else
+ {
+ fault = new ReservedInstructionFault();
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ //If there are 2 Destination Registers then
+ //concatenate the values for the traceData
+ if(traceData && _numDestRegs == 2) {
+ // FIXME - set the trace value correctly here
+ //uint64_t hilo_final_val = (uint64_t)HI_RD_SEL << 32 | LO_RD_SEL;
+ //traceData->setData(hilo_final_val);
+ }
+ }
+ return fault;
+ }
+}};
+
+//Outputs to decoder.cc
+output decoder {{
+}};
+
+output exec {{
+ bool isDspEnabled(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 )
+ return false;
+#else
+ //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n");
+#endif
+ return true;
+ }
+}};
+
+output exec {{
+ bool isDspPresent(%(CPU_exec_context)s *xc)
+ {
+#if FULL_SYSTEM
+ if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 )
+ return false;
+#else
+ //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n");
+#endif
+ return true;
+ }
+}};
+
+// add code to fetch the DSPControl register
+// and write it back after execution, giving
+// the instruction the opportunity to modify
+// it if necessary
+def format DspIntOp(code, *opt_flags) {{
+
+ decl_code = 'uint32_t dspctl;\n'
+ decl_code += 'dspctl = DSPControl;\n'
+
+ write_code = 'DSPControl = dspctl;\n'
+
+ code = decl_code + code + write_code
+
+ iop = InstObjParams(name, Name, 'DspIntOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = DspExecute.subst(iop)
+}};
+
+// add code to fetch the DSPControl register
+// and write it back after execution, giving
+// the instruction the opportunity to modify
+// it if necessary; also, fetch the appropriate
+// HI/LO register pair, based on the AC
+// instruction field.
+
+def format DspHiLoOp(code, *opt_flags) {{
+
+ decl_code = 'int64_t dspac;\n'
+ decl_code += 'uint32_t dspctl;\n'
+
+ fetch_code = 'dspctl = DSPControl;\n'
+ fetch_code += 'dspac = HI_RD_SEL;\n'
+ fetch_code += 'dspac = dspac << 32 | LO_RD_SEL;\n'
+
+ write_code = 'DSPControl = dspctl;\n'
+ write_code += 'HI_RD_SEL = dspac<63:32>;\n'
+ write_code += 'LO_RD_SEL = dspac<31:0>;\n'
+
+ code = decl_code + fetch_code + code + write_code
+
+ iop = InstObjParams(name, Name, 'DspHiLoOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = DspHiLoExecute.subst(iop)
+
+}};
+
+
+
diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa
index 4c3eec132..1cff9732f 100644
--- a/src/arch/mips/isa/formats/formats.isa
+++ b/src/arch/mips/isa/formats/formats.isa
@@ -44,6 +44,9 @@
//Include the integer formats
##include "int.isa"
+//Include the DSP integer format
+##include "dsp.isa"
+
//Include the floatOp format
##include "fp.isa"
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index ac6805cc7..4b340e2e6 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -87,6 +87,12 @@ output decoder {{
}};
output exec {{
+ inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+ {
+ //@TODO: Implement correct CP0 checks to see if the CP1
+ // unit is enable or not
+ return NoFault;
+ }
//If any operand is Nan return the appropriate QNaN
template <class T>
@@ -145,7 +151,7 @@ output exec {{
uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
//Write FCSR from FloatRegFile
- cpu->tcBase()->setFloatRegBits(FCSR, genInvalidVector(fcsr_bits));
+ cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits));
if (traceData) { traceData->setData(mips_nan); }
return true;
@@ -160,6 +166,7 @@ output exec {{
//Read FCSR from FloatRegFile
uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR);
+ // TODO: Use utility function here
fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0);
//Write FCSR from FloatRegFile
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 2f131f6d9..7fa8e4817 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -34,6 +34,7 @@
//
output header {{
#include <iostream>
+ using namespace std;
/**
* Base class for integer operations.
*/
@@ -64,12 +65,12 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
- class HiLoMiscOp: public HiLoOp
+ class HiLoRsSelOp: public HiLoOp
{
protected:
/// Constructor
- HiLoMiscOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoRsSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
HiLoOp(mnem, _machInst, __opClass)
{
}
@@ -77,6 +78,31 @@ output header {{
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+ class HiLoRdSelOp: public HiLoOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoRdSelOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
+
+ class HiLoRdSelValOp: public HiLoOp
+ {
+ protected:
+
+ /// Constructor
+ HiLoRdSelValOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ HiLoOp(mnem, _machInst, __opClass)
+ {
+ }
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ };
class IntImmOp : public MipsStaticInst
{
@@ -105,9 +131,7 @@ output header {{
}};
-// HiLo<Misc> instruction class execute method template.
-// Mainly to get instruction trace data to print out
-// correctly
+// HiLo instruction class execute method template.
def template HiLoExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
@@ -121,12 +145,58 @@ def template HiLoExecute {{
if(fault == NoFault)
{
%(op_wb)s;
- //If there are 2 Destination Registers then
- //concatenate the values for the traceData
- if(traceData && _numDestRegs == 2) {
- uint64_t hilo_final_val = (uint64_t)HI << 32 | LO;
- traceData->setData(hilo_final_val);
- }
+ }
+ return fault;
+ }
+}};
+
+// HiLoRsSel instruction class execute method template.
+def template HiLoRsSelExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if( ACSRC > 0 && !isDspEnabled(xc) )
+ {
+ fault = new DspStateDisabledFault();
+ }
+ else
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
+ }
+}};
+
+// HiLoRdSel instruction class execute method template.
+def template HiLoRdSelExecute {{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+
+ %(op_decl)s;
+
+ if( ACDST > 0 && !isDspEnabled(xc) )
+ {
+ fault = new DspStateDisabledFault();
+ }
+ else
+ {
+ %(op_rd)s;
+ %(code)s;
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
}
return fault;
}
@@ -181,7 +251,37 @@ output decoder {{
return ss.str();
}
- std::string HiLoMiscOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ std::string HiLoRsSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ printReg(ss, _destRegIdx[0]);
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
+ std::string HiLoRdSelOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ ccprintf(ss, "%-10s ", mnemonic);
+
+ if (_numDestRegs > 0 && _destRegIdx[0] < 32) {
+ printReg(ss, _destRegIdx[0]);
+ } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) {
+ printReg(ss, _srcRegIdx[0]);
+ }
+
+ return ss.str();
+ }
+
+ std::string HiLoRdSelValOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
@@ -239,26 +339,43 @@ def format IntImmOp(code, *opt_flags) {{
exec_output = BasicExecute.subst(iop)
}};
-def format HiLoOp(code, *opt_flags) {{
- code += 'HI = val<63:32>;\n'
- code += 'LO = val<31:0>;\n'
-
- iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
+def format HiLoRsSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRsSelOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = HiLoExecute.subst(iop)
+ exec_output = HiLoRsSelExecute.subst(iop)
}};
-def format HiLoMiscOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'HiLoMiscOp', code, opt_flags)
+def format HiLoRdSelOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
}};
+def format HiLoRdSelValOp(code, *opt_flags) {{
+ if '.sd' in code:
+ code = 'int64_t ' + code
+ elif '.ud' in code:
+ code = 'uint64_t ' + code
+ code += 'HI_RD_SEL = val<63:32>;\n'
+ code += 'LO_RD_SEL = val<31:0>;\n'
+ iop = InstObjParams(name, Name, 'HiLoRdSelOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoRdSelExecute.subst(iop)
+}};
+def format HiLoOp(code, *opt_flags) {{
+ iop = InstObjParams(name, Name, 'HiLoOp', code, opt_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = HiLoExecute.subst(iop)
+}};
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index df80e7a1f..c8e85a754 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -69,6 +69,8 @@ output header {{
const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
const StaticInstPtr &memAccInst() const { return memAccPtr; }
+
+ unsigned memAccFlags() { return memAccessFlags; }
};
/**
@@ -108,6 +110,37 @@ output decoder {{
flags[IsFloating] ? FD : RD,
RS, RT);
}
+
+}};
+
+output exec {{
+ /** return data in cases where there the size of data is only
+ known in the packet
+ */
+ uint64_t getStoreData(Packet *packet) {
+ switch (packet->getSize())
+ {
+ case 8:
+ return packet->get<uint8_t>();
+
+ case 16:
+ return packet->get<uint16_t>();
+
+ case 32:
+ return packet->get<uint32_t>();
+
+ case 864:
+ return packet->get<uint64_t>();
+
+ default:
+ std::cerr << "bad store data size = " << packet->getSize() << std::endl;
+
+ assert(0);
+ return 0;
+ }
+ }
+
+
}};
def template LoadStoreDeclare {{
@@ -125,7 +158,7 @@ def template LoadStoreDeclare {{
{
public:
/// Constructor
- EAComp(MachInst machInst);
+ EAComp(ExtMachInst machInst);
%(BasicExecDeclare)s
};
@@ -137,7 +170,7 @@ def template LoadStoreDeclare {{
{
public:
/// Constructor
- MemAcc(MachInst machInst);
+ MemAcc(ExtMachInst machInst);
%(BasicExecDeclare)s
};
@@ -145,13 +178,15 @@ def template LoadStoreDeclare {{
public:
/// Constructor.
- %(class_name)s(MachInst machInst);
+ %(class_name)s(ExtMachInst machInst);
%(BasicExecDeclare)s
%(InitiateAccDeclare)s
%(CompleteAccDeclare)s
+
+ %(MemAccSizeDeclare)s
};
}};
@@ -162,15 +197,18 @@ def template InitiateAccDeclare {{
def template CompleteAccDeclare {{
- Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault completeAcc(Packet *, %(CPU_exec_context)s *, Trace::InstRecord *) const;
}};
+def template MemAccSizeDeclare {{
+ int memAccSize(%(CPU_exec_context)s *xc);
+}};
def template EACompConstructor {{
/** TODO: change op_class to AddrGenOp or something (requires
* creating new member of OpClass enum in op_class.hh, updating
* config files, etc.). */
- inline %(class_name)s::EAComp::EAComp(MachInst machInst)
+ inline %(class_name)s::EAComp::EAComp(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
{
%(constructor)s;
@@ -179,7 +217,7 @@ def template EACompConstructor {{
def template MemAccConstructor {{
- inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
+ inline %(class_name)s::MemAcc::MemAcc(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
{
%(constructor)s;
@@ -188,7 +226,7 @@ def template MemAccConstructor {{
def template LoadStoreConstructor {{
- inline %(class_name)s::%(class_name)s(MachInst machInst)
+ inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
new EAComp(machInst), new MemAcc(machInst))
{
@@ -210,8 +248,8 @@ def template EACompExecute {{
%(op_rd)s;
%(ea_code)s;
+ // NOTE: Trace Data is written using execute or completeAcc templates
if (fault == NoFault) {
- %(op_wb)s;
xc->setEA(EA);
}
@@ -227,19 +265,16 @@ def template LoadMemAccExecute {{
Addr EA;
Fault fault = NoFault;
- %(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
+
EA = xc->getEA();
- if (fault == NoFault) {
- fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- %(memacc_code)s;
- }
+ fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
- if (fault == NoFault) {
- %(op_wb)s;
- }
+ %(memacc_code)s;
+
+ // NOTE: Write back data using execute or completeAcc templates
return fault;
}
@@ -292,9 +327,8 @@ def template LoadInitiateAcc {{
}
}};
-
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -302,6 +336,7 @@ def template LoadCompleteAcc {{
%(fp_enable_check)s;
%(op_decl)s;
+ %(op_rd)s;
Mem = pkt->get<typeof(Mem)>();
@@ -318,6 +353,15 @@ def template LoadCompleteAcc {{
}};
+
+def template LoadStoreMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ // Return the memory access size in bytes
+ return (%(mem_acc_size)d / 8);
+ }
+}};
+
def template StoreMemAccExecute {{
Fault
%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
@@ -325,10 +369,12 @@ def template StoreMemAccExecute {{
{
Addr EA;
Fault fault = NoFault;
+ uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
+
EA = xc->getEA();
if (fault == NoFault) {
@@ -337,16 +383,9 @@ def template StoreMemAccExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
- }
-
- if (fault == NoFault) {
- %(postacc_code)s;
- }
-
- if (fault == NoFault) {
- %(op_wb)s;
+ memAccessFlags, &write_result);
+ // @NOTE: Need to Call Complete Access to Set Trace Data
+ //if (traceData) { traceData->setData(Mem); }
}
return fault;
@@ -389,13 +428,13 @@ def template StoreCondMemAccExecute {{
}
}};
-
def template StoreExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
+ uint64_t write_result = 0;
%(fp_enable_check)s;
%(op_decl)s;
@@ -408,7 +447,7 @@ def template StoreExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
- memAccessFlags, NULL);
+ memAccessFlags, &write_result);
if (traceData) { traceData->setData(Mem); }
}
@@ -487,7 +526,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -502,6 +541,8 @@ def template StoreCompleteAcc {{
if (fault == NoFault) {
%(op_wb)s;
+
+ if (traceData) { traceData->setData(getStoreData(pkt)); }
}
return fault;
@@ -509,7 +550,7 @@ def template StoreCompleteAcc {{
}};
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -584,7 +625,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
+ Fault %(class_name)s::completeAcc(Packet *pkt,
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
@@ -594,6 +635,15 @@ def template MiscCompleteAcc {{
}
}};
+
+def template MiscMemAccSize {{
+ int %(class_name)s::memAccSize(%(CPU_exec_context)s *xc)
+ {
+ panic("Misc instruction does not support split access method!");
+ return 0;
+ }
+}};
+
def format LoadMemory(memacc_code, ea_code = {{ EA = Rs + disp; }},
mem_flags = [], inst_flags = []) {{
(header_output, decoder_output, decode_block, exec_output) = \
@@ -650,6 +700,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3;
decl_code += '\tbyte_offset ^= 3;\n'
decl_code += '#endif\n'
decl_code += 'fault = xc->read(EA, (uint32_t&)mem_word, memAccessFlags);\n'
+ #decl_code += 'xc->readFunctional(EA,(uint32_t&)mem_word);'
memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n'
(header_output, decoder_output, decode_block, exec_output) = \
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index d7240335e..b3520050a 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -37,46 +37,185 @@ output header {{
/**
* Base class for MIPS MT ASE operations.
*/
- class MT : public MipsStaticInst
+ class MTOp : public MipsStaticInst
{
protected:
/// Constructor
- MT(const char *mnem, MachInst _machInst, OpClass __opClass) :
- MipsStaticInst(mnem, _machInst, __opClass)
+ MTOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MipsStaticInst(mnem, _machInst, __opClass), user_mode(false)
{
}
- std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+
+ bool user_mode;
+ };
+
+ class MTUserModeOp : public MTOp
+ {
+ protected:
+
+ /// Constructor
+ MTUserModeOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+ MTOp(mnem, _machInst, __opClass)
+ {
+ user_mode = true;
+ }
+
+ //std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
}};
output decoder {{
- //Edit This Template When MT is Implemented
- std::string MT::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return "Disassembly of MT instruction\n";
+ std::string MTOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+ {
+ std::stringstream ss;
+
+ if (mnemonic == "mttc0" || mnemonic == "mftc0") {
+ ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
+ } else if (mnemonic == "mftgpr") {
+ ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
+ } else {
+ ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
}
+
+ return ss.str();
+ }
}};
-def template MTExecute {{
- //Edit This Template When MT is Implemented
+output exec {{
+ void getThrRegExValues(%(CPU_exec_context)s *xc, unsigned &vpe_conf0, unsigned &tc_bind_mt, unsigned &tc_bind, unsigned &vpe_control, unsigned &mvp_conf0)
+ {
+ vpe_conf0 = xc->readMiscReg(VPEConf0);
+ tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag);
+ tc_bind = xc->readMiscReg(TCBind);
+ vpe_control = xc->readMiscReg(VPEControl);
+ mvp_conf0 = xc->readMiscReg(MVPConf0);
+ }
+
+ void getMTExValues(%(CPU_exec_context)s *xc, unsigned &config3)
+ {
+ config3 = xc->readMiscReg(Config3_MT);
+ }
+}};
+
+def template ThreadRegisterExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
- //Write the resulting state to the execution context
+ Fault fault = NoFault;
+ int64_t data;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ unsigned vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0;
+
+ getThrRegExValues(xc, vpe_conf0, tc_bind_mt, tc_bind, vpe_control, mvp_conf0);
+
+ if (isCoprocessorEnabled(xc, 0)) {
+ if (bits(vpe_conf0, VPEC0_MVP) == 0 &&
+ bits(tc_bind_mt, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO) !=
+ bits(tc_bind, TCB_CUR_VPE_HI, TCB_CUR_VPE_LO)) {
+ data = -1;
+ } else if (bits(vpe_control, VPEC_TARG_TC_HI, VPEC_TARG_TC_LO) >
+ bits(mvp_conf0, MVPC0_PTC_HI, MVPC0_PTC_LO)) {
+ data = -1;
+ } else {
+ int top_bit = 0;
+ int bottom_bit = 0;
+
+ if (MT_H == 1) {
+ top_bit = 63;
+ bottom_bit = 32;
+ } else {
+ top_bit = 31;
+ bottom_bit = 0;
+ }
+
+ %(code)s;
+ }
+ } else {
+ fault = new CoprocessorUnusableFault();
+ }
+
+ if(fault == NoFault)
+ {
%(op_wb)s;
+ }
- //Call into the trap handler with the appropriate fault
- return No_Fault;
+ return fault;
+ }
+}};
+
+def template MTExecute{{
+ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+ {
+ Fault fault = NoFault;
+ %(op_decl)s;
+ %(op_rd)s;
+
+ unsigned config3;
+
+ getMTExValues(xc, config3);
+
+ if (isCoprocessorEnabled(xc, 0)) {
+ if (bits(config3, CFG3_MT) == 1) {
+ %(code)s;
+ } else {
+ fault = new ReservedInstructionFault();
+ }
+ } else {
+ fault = new CoprocessorUnusableFault();
+ }
+
+ if(fault == NoFault)
+ {
+ %(op_wb)s;
+ }
+ return fault;
}
}};
// Primary format for integer operate instructions:
-def format MipsMT() {{
- code = 'panic(\"Mips MT Is Currently Unimplemented.\");\n'
- iop = InstObjParams(name, Name, 'MT', code)
+def format MT_Control(code, *opt_flags) {{
+ inst_flags = ('IsNonSpeculative', )
+ op_type = 'MTOp'
+
+ for x in opt_flags:
+ if x == 'UserMode':
+ op_type = 'MTUserModeOp'
+ else:
+ inst_flags += (x, )
+
+ iop = InstObjParams(name, Name, op_type, code, inst_flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = MTExecute.subst(iop)
+}};
+
+def format MT_MFTR(code, *flags) {{
+ flags += ('IsNonSpeculative', )
+# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+
+ code += 'if (MT_H == 1) {\n'
+ code += 'data = bits(data, top_bit, bottom_bit);\n'
+ code += '}\n'
+ code += 'Rd = data;\n'
+
+ iop = InstObjParams(name, Name, 'MTOp', code, flags)
+ header_output = BasicDeclare.subst(iop)
+ decoder_output = BasicConstructor.subst(iop)
+ decode_block = BasicDecode.subst(iop)
+ exec_output = ThreadRegisterExecute.subst(iop)
+}};
+
+def format MT_MTTR(code, *flags) {{
+ flags += ('IsNonSpeculative', )
+# code = 'std::cerr << curTick << \": T\" << xc->tcBase()->getThreadNum() << \": Executing MT INST: ' + name + '\" << endl;\n' + code
+ iop = InstObjParams(name, Name, 'MTOp', code, flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = BasicExecute.subst(iop)
+ exec_output = ThreadRegisterExecute.subst(iop)
}};
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index dbfbb8ce1..b6db7864f 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -70,7 +70,9 @@ def template TlbOpExecute {{
// Primary format for integer operate instructions:
def format TlbOp(code, *opt_flags) {{
- iop = InstObjParams(name, Name, 'MipsStaticInst', code, opt_flags)
+ orig_code = code
+ cblk = code
+ iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecodeWithMnemonic.subst(iop)
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 884e6f727..eea616568 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -88,7 +88,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
+ completeAccTemplate.subst(iop))
}};
-
output header {{
std::string inst2string(MachInst machInst);
}};
@@ -97,7 +96,7 @@ output decoder {{
std::string inst2string(MachInst machInst)
{
- std::string str = "";
+ string str = "";
uint32_t mask = 0x80000000;
for(int i=0; i < 32; i++) {
@@ -114,40 +113,3 @@ std::string inst2string(MachInst machInst)
}
}};
-output exec {{
-
- using namespace MipsISA;
-
- /// CLEAR ALL CPU INST/EXE HAZARDS
- inline void
- clear_exe_inst_hazards()
- {
- //CODE HERE
- }
-
-
- /// Check "FP enabled" machine status bit. Called when executing any FP
- /// instruction in full-system mode.
- /// @retval Full-system mode: NoFault if FP is enabled, FenFault
- /// if not. Non-full-system mode: always returns NoFault.
-#if FULL_SYSTEM
- inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
- {
- Fault fault = NoFault; // dummy... this ipr access should not fault
- if (!Mips34k::ICSR_FPE(xc->readIpr(MipsISA::IPR_ICSR, fault))) {
- fault = FloatEnableFault;
- }
- return fault;
- }
-#else
- inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
- {
- return NoFault;
- }
-#endif
-
-
-
-}};
-
-