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| author | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2010-01-19 15:48:12 -0600 |
| commit | 279f179babc9e5663156777c533c06edc91bce9a (patch) | |
| tree | e6718ee514cc81678491b50562ce8c463c0b20fd /src/arch/mips/isa/formats | |
| parent | 5aa104e072eb20f6aca49b169521b0c2da33c844 (diff) | |
| parent | 295516a590b6e47c9a881f193027447e500c749c (diff) | |
| download | gem5-279f179babc9e5663156777c533c06edc91bce9a.tar.xz | |
merge
Diffstat (limited to 'src/arch/mips/isa/formats')
| -rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index adcb16137..161a52b06 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -619,7 +619,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; def format Prefetch(ea_code = {{ EA = Rs + disp; }}, mem_flags = [], pf_flags = [], inst_flags = []) {{ - pf_mem_flags = mem_flags + pf_flags + ['NO_FAULT'] + pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp'] |