diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:22 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-08 13:58:22 -0600 |
| commit | cdacbe734a9e6e0f20e0a37ef694995373b83f66 (patch) | |
| tree | 775ea93dcd7acd5255818739ac78523634c8cc62 /src/arch/mips/isa/formats | |
| parent | f4f5d03ed211571f07f13ea9d5df0d70f3101aa3 (diff) | |
| download | gem5-cdacbe734a9e6e0f20e0a37ef694995373b83f66.tar.xz | |
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.
On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.
On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
Diffstat (limited to 'src/arch/mips/isa/formats')
| -rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index e7dbd8e9b..c4666e4ab 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -452,7 +452,7 @@ def template MiscExecute {{ Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - Addr EA; + Addr EA M5_VAR_USED = 0; Fault fault = NoFault; %(fp_enable_check)s; @@ -577,12 +577,11 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; def format Prefetch(ea_code = {{ EA = Rs + disp; }}, mem_flags = [], pf_flags = [], inst_flags = []) {{ pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] - pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', - 'IsDataPrefetch', 'MemReadOp'] + pf_inst_flags = inst_flags (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, ea_code, - 'xc->prefetch(EA, memAccessFlags);', + 'warn_once("Prefetching not implemented for MIPS\\n");', pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') }}; |