diff options
| author | Nathanael Premillieu <nathanael.premillieu@arm.com> | 2017-04-05 12:46:06 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch) | |
| tree | 7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/mips/isa/formats | |
| parent | 864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff) | |
| download | gem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz | |
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.
Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/mips/isa/formats')
| -rw-r--r-- | src/arch/mips/isa/formats/int.isa | 12 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/mt.isa | 3 |
2 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index 52358bbdb..641608e89 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -257,9 +257,9 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); - if (_numDestRegs > 0 && _destRegIdx[0] < 32) { + if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { + } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { printReg(ss, _srcRegIdx[0]); } @@ -272,9 +272,9 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); - if (_numDestRegs > 0 && _destRegIdx[0] < 32) { + if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { + } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { printReg(ss, _srcRegIdx[0]); } @@ -287,9 +287,9 @@ output decoder {{ ccprintf(ss, "%-10s ", mnemonic); - if (_numDestRegs > 0 && _destRegIdx[0] < 32) { + if (_numDestRegs > 0 && _destRegIdx[0].regIdx < 32) { printReg(ss, _destRegIdx[0]); - } else if (_numSrcRegs > 0 && _srcRegIdx[0] < 32) { + } else if (_numSrcRegs > 0 && _srcRegIdx[0].regIdx < 32) { printReg(ss, _srcRegIdx[0]); } diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 8d2254cb4..b34773ef5 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -102,7 +102,8 @@ output exec {{ MVPConf0Reg &mvp_conf0) { vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); - tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base); + tc_bind_mt = xc->readRegOtherThread(RegId(MiscRegClass, + MISCREG_TC_BIND)); tc_bind = xc->readMiscReg(MISCREG_TC_BIND); vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); |