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author | Gabe Black <gblack@eecs.umich.edu> | 2011-09-26 23:48:54 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2011-09-26 23:48:54 -0700 |
commit | 997cbe1c09f6ffff6bee11bb374e3a32601d0f06 (patch) | |
tree | 64c6ed0b94a0f6becb47b04f4e4d0e5b2f9c59fc /src/arch/mips/isa/formats | |
parent | 56bddab18940e766bdfdeb98e0691a994859dcde (diff) | |
download | gem5-997cbe1c09f6ffff6bee11bb374e3a32601d0f06.tar.xz |
ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.
By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.
Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
Diffstat (limited to 'src/arch/mips/isa/formats')
-rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 36 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/int.isa | 4 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 2 |
3 files changed, 21 insertions, 21 deletions
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index dcea32a36..f99d2327e 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -217,20 +217,20 @@ def format FloatCompareOp(cond_code, *flags) {{ import sys code = 'bool cond;\n' - if '.sf' in cond_code or 'SinglePrecision' in flags: + if '_sf' in cond_code or 'SinglePrecision' in flags: if 'QnanException' in flags: - code += 'if (isQnan(&Fs.sf, 32) || isQnan(&Ft.sf, 32)) {\n' + code += 'if (isQnan(&Fs_sf, 32) || isQnan(&Ft_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\treturn NoFault;' code += '}\n else ' - code += 'if (isNan(&Fs.sf, 32) || isNan(&Ft.sf, 32)) {\n' - elif '.df' in cond_code or 'DoublePrecision' in flags: + code += 'if (isNan(&Fs_sf, 32) || isNan(&Ft_sf, 32)) {\n' + elif '_df' in cond_code or 'DoublePrecision' in flags: if 'QnanException' in flags: - code += 'if (isQnan(&Fs.df, 64) || isQnan(&Ft.df, 64)) {\n' + code += 'if (isQnan(&Fs_df, 64) || isQnan(&Ft_df, 64)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += '\treturn NoFault;' code += '}\n else ' - code += 'if (isNan(&Fs.df, 64) || isNan(&Ft.df, 64)) {\n' + code += 'if (isNan(&Fs_df, 64) || isNan(&Ft_df, 64)) {\n' else: sys.exit('Decoder Failed: Can\'t Determine Operand Type\n') @@ -257,16 +257,16 @@ def format FloatConvertOp(code, *flags) {{ #Determine Source Type convert = 'fpConvert(' - if '.sf' in code: + if '_sf' in code: code = 'float ' + code + '\n' convert += 'SINGLE_TO_' - elif '.df' in code: + elif '_df' in code: code = 'double ' + code + '\n' convert += 'DOUBLE_TO_' - elif '.uw' in code: + elif '_uw' in code: code = 'uint32_t ' + code + '\n' convert += 'WORD_TO_' - elif '.ud' in code: + elif '_ud' in code: code = 'uint64_t ' + code + '\n' convert += 'LONG_TO_' else: @@ -274,13 +274,13 @@ def format FloatConvertOp(code, *flags) {{ #Determine Destination Type if 'ToSingle' in flags: - code += 'Fd.uw = ' + convert + 'SINGLE, ' + code += 'Fd_uw = ' + convert + 'SINGLE, ' elif 'ToDouble' in flags: - code += 'Fd.ud = ' + convert + 'DOUBLE, ' + code += 'Fd_ud = ' + convert + 'DOUBLE, ' elif 'ToWord' in flags: - code += 'Fd.uw = ' + convert + 'WORD, ' + code += 'Fd_uw = ' + convert + 'WORD, ' elif 'ToLong' in flags: - code += 'Fd.ud = ' + convert + 'LONG, ' + code += 'Fd_ud = ' + convert + 'LONG, ' else: sys.exit("Error Determining Destination Type for Conversion") @@ -328,17 +328,17 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ code += 'code_block1 = code_block2 = true;\n' if 'QnanException' in flags: - code += 'if (isQnan(&Fs1.sf, 32) || isQnan(&Ft1.sf, 32)) {\n' + code += 'if (isQnan(&Fs1_sf, 32) || isQnan(&Ft1_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += 'code_block1 = false;' code += '}\n' - code += 'if (isQnan(&Fs2.sf, 32) || isQnan(&Ft2.sf, 32)) {\n' + code += 'if (isQnan(&Fs2_sf, 32) || isQnan(&Ft2_sf, 32)) {\n' code += '\tFCSR = genInvalidVector(FCSR);\n' code += 'code_block2 = false;' code += '}\n' code += 'if (code_block1) {' - code += '\tif (isNan(&Fs1.sf, 32) || isNan(&Ft1.sf, 32)) {\n' + code += '\tif (isNan(&Fs1_sf, 32) || isNan(&Ft1_sf, 32)) {\n' if 'UnorderedTrue' in flags: code += 'cond1 = 1;\n' elif 'UnorderedFalse' in flags: @@ -350,7 +350,7 @@ def format FloatPSCompareOp(cond_code1, cond_code2, *flags) {{ code += 'FCSR = genCCVector(FCSR, CC, cond1);}\n}\n' code += 'if (code_block2) {' - code += '\tif (isNan(&Fs2.sf, 32) || isNan(&Ft2.sf, 32)) {\n' + code += '\tif (isNan(&Fs2_sf, 32) || isNan(&Ft2_sf, 32)) {\n' if 'UnorderedTrue' in flags: code += 'cond2 = 1;\n' elif 'UnorderedFalse' in flags: diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa index 88ff5c1d3..14dcc7259 100644 --- a/src/arch/mips/isa/formats/int.isa +++ b/src/arch/mips/isa/formats/int.isa @@ -357,9 +357,9 @@ def format HiLoRdSelOp(code, *opt_flags) {{ def format HiLoRdSelValOp(code, *opt_flags) {{ - if '.sd' in code: + if '_sd' in code: code = 'int64_t ' + code - elif '.ud' in code: + elif '_ud' in code: code = 'uint64_t ' + code code += 'HI_RD_SEL = val<63:32>;\n' diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 22296bc3b..0ef2ac6ae 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -543,7 +543,7 @@ def format StoreFPIndexedMemory(memacc_code, ea_code = {{ EA = Rs + Rt; }}, def format LoadUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; }}, mem_flags = [], inst_flags = []) {{ decl_code = ''' - uint32_t mem_word = Mem.uw; + uint32_t mem_word = Mem_uw; uint32_t unalign_addr = Rs + disp; uint32_t byte_offset = unalign_addr & 3; if (GuestByteOrder == BigEndianByteOrder) |