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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-21 23:38:26 -0700 |
commit | c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9 (patch) | |
tree | 3a6c277e4c65b041de01b7b976a60c245729ec65 /src/arch/mips/isa/formats | |
parent | c635d04642723f7dea68ee6c6c882c7751d8484b (diff) | |
download | gem5-c874bfae3fd8dfeb05f4b35eba614ffe0145dfa9.tar.xz |
MIPS: Format the register index constants like the other ISAs.
Also a few more style fixes.
Diffstat (limited to 'src/arch/mips/isa/formats')
-rw-r--r-- | src/arch/mips/isa/formats/control.isa | 10 | ||||
-rwxr-xr-x | src/arch/mips/isa/formats/dsp.isa | 4 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/fp.isa | 9 | ||||
-rw-r--r-- | src/arch/mips/isa/formats/mt.isa | 12 |
4 files changed, 18 insertions, 17 deletions
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index c8eddb1ad..cb5b4372f 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -180,12 +180,12 @@ output exec {{ #if !FULL_SYSTEM return true; #else - MiscReg Stat = xc->readMiscReg(MipsISA::Status); + MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); switch(cop_num) { case 0: { - MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); + MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -216,8 +216,8 @@ output exec {{ bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - MiscReg Stat = xc->readMiscRegNoEffect(MipsISA::Status); - MiscReg Dbg = xc->readMiscRegNoEffect(MipsISA::Debug); + MiscReg Stat = xc->readMiscRegNoEffect(MISCREG_STATUS); + MiscReg Dbg = xc->readMiscRegNoEffect(MISCREG_DEBUG); if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode @@ -232,7 +232,7 @@ output exec {{ bool isMMUTLB(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if((xc->readMiscRegNoEffect(MipsISA::Config) & 0x00000380)==0x80) + if((xc->readMiscRegNoEffect(MISCREG_CONFIG) & 0x00000380)==0x80) return true; #endif return false; diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa index 1874d37b2..7d16b4162 100755 --- a/src/arch/mips/isa/formats/dsp.isa +++ b/src/arch/mips/isa/formats/dsp.isa @@ -143,7 +143,7 @@ output exec {{ bool isDspEnabled(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Status), 24, 24 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_STATUS), 24, 24 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspEnabled() check defaults to TRUE\n"); @@ -156,7 +156,7 @@ output exec {{ bool isDspPresent(%(CPU_exec_context)s *xc) { #if FULL_SYSTEM - if( bits( xc->readMiscReg(MipsISA::Config3), 10, 10 ) == 0 ) + if( bits( xc->readMiscReg(MISCREG_CONFIG3), 10, 10 ) == 0 ) return false; #else //printf("Syscall Emulation Mode: isDspPresent() check defaults to TRUE\n"); diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa index 52fcd0724..72d87f997 100644 --- a/src/arch/mips/isa/formats/fp.isa +++ b/src/arch/mips/isa/formats/fp.isa @@ -135,12 +135,13 @@ output exec {{ cpu->setFloatRegOperandBits(inst, 0, mips_nan); //Read FCSR from FloatRegFile - uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr_bits = + cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); uint32_t new_fcsr = genInvalidVector(fcsr_bits); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, new_fcsr); if (traceData) { traceData->setData(mips_nan); } return true; @@ -153,13 +154,13 @@ output exec {{ fpResetCauseBits(%(CPU_exec_context)s *cpu) { //Read FCSR from FloatRegFile - uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FCSR); + uint32_t fcsr = cpu->tcBase()->readFloatRegBits(FLOATREG_FCSR); // TODO: Use utility function here fcsr = bits(fcsr, 31, 18) << 18 | bits(fcsr, 11, 0); //Write FCSR from FloatRegFile - cpu->tcBase()->setFloatRegBits(FCSR, fcsr); + cpu->tcBase()->setFloatRegBits(FLOATREG_FCSR, fcsr); } }}; diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index 4f2d33709..9d354c46a 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -90,16 +90,16 @@ output exec {{ TCBindReg &tc_bind, VPEControlReg &vpe_control, MVPConf0Reg &mvp_conf0) { - vpe_conf0 = xc->readMiscReg(VPEConf0); - tc_bind_mt = xc->readRegOtherThread(TCBind + Ctrl_Base_DepTag); - tc_bind = xc->readMiscReg(TCBind); - vpe_control = xc->readMiscReg(VPEControl); - mvp_conf0 = xc->readMiscReg(MVPConf0); + vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); + tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); + tc_bind = xc->readMiscReg(MISCREG_TC_BIND); + vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); + mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); } void getMTExValues(%(CPU_exec_context)s *xc, Config3Reg &config3) { - config3 = xc->readMiscReg(Config3); + config3 = xc->readMiscReg(MISCREG_CONFIG3); } }}; |