Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

src/base/traceflags.py:
    Hand merge.

--HG--
extra : convert_revision : 9e7539eeab4220ed7a7237457a8f336f79216924

1 files changed, 63 insertions, 8 deletions

diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa
index 3843dc053..b89eb5249 100644
--- a/src/arch/mips/isa/operands.isa
+++ b/src/arch/mips/isa/operands.isa
@@ -48,16 +48,37 @@ def operands {{
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
     'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
 
+    #Immediate Value operand
+    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+
     #Operands used for Link or Syscall Insts
     'R31': ('IntReg', 'uw','31','IsInteger', 4),
     'R2':  ('IntReg', 'uw','2', 'IsInteger', 5),
 
     #Special Integer Reg operands
-    'HI':  ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 6),
-    'LO':  ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 7),
+    'LO0':  ('IntReg', 'uw','MipsISA::LO', 'IsInteger', 6),
+    'HI0':  ('IntReg', 'uw','MipsISA::HI', 'IsInteger', 7),
 
-    #Immediate Value operand
-    'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
+    #Bitfield-dependent HI/LO Register Access
+    'LO_RD_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACDST*3', None, 6),
+    'HI_RD_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACDST*3', None, 7),
+    'LO_RS_SEL': ('IntReg','uw','MipsISA::DSPLo0 + ACSRC*3', None, 6),
+    'HI_RS_SEL': ('IntReg','uw','MipsISA::DSPHi0 + ACSRC*3', None, 7),
+
+    #DSP Special Purpose Integer Operands
+    'DSPControl': ('IntReg', 'uw', 'MipsISA::DSPControl', None, 8),
+    'DSPLo0': ('IntReg', 'uw', 'MipsISA::LO', None, 1),
+    'DSPHi0': ('IntReg', 'uw', 'MipsISA::HI', None, 1),
+    'DSPACX0': ('IntReg', 'uw', 'MipsISA::DSPACX0', None, 1),
+    'DSPLo1': ('IntReg', 'uw', 'MipsISA::DSPLo1', None, 1),
+    'DSPHi1': ('IntReg', 'uw', 'MipsISA::DSPHi1', None, 1),
+    'DSPACX1': ('IntReg', 'uw', 'MipsISA::DSPACX1', None, 1),
+    'DSPLo2': ('IntReg', 'uw', 'MipsISA::DSPLo2', None, 1),
+    'DSPHi2': ('IntReg', 'uw', 'MipsISA::DSPHi2', None, 1),
+    'DSPACX2': ('IntReg', 'uw', 'MipsISA::DSPACX2', None, 1),
+    'DSPLo3': ('IntReg', 'uw', 'MipsISA::DSPLo3', None, 1),
+    'DSPHi3': ('IntReg', 'uw', 'MipsISA::DSPHi3', None, 1),
+    'DSPACX3': ('IntReg', 'uw', 'MipsISA::DSPACX3', None, 1),
 
     #Floating Point Reg Operands
     'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
@@ -65,14 +86,14 @@ def operands {{
     'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
     'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
 
-    #Special Floating Point Control Reg Operands
+    #Special Purpose Floating Point Control Reg Operands
     'FIR':  ('FloatReg', 'uw', 'MipsISA::FIR', 'IsFloating', 1),
     'FCCR': ('FloatReg', 'uw', 'MipsISA::FCCR', 'IsFloating', 2),
     'FEXR': ('FloatReg', 'uw', 'MipsISA::FEXR', 'IsFloating', 3),
     'FENR': ('FloatReg', 'uw', 'MipsISA::FENR', 'IsFloating', 3),
     'FCSR': ('FloatReg', 'uw', 'MipsISA::FCSR', 'IsFloating', 3),
 
-     #Operands For Paired Singles FP Operations
+    #Operands For Paired Singles FP Operations
     'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
     'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
     'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
@@ -82,10 +103,44 @@ def operands {{
     'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
     'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
 
+    #Status Control Reg
+    'Status': ('ControlReg', 'uw', 'MipsISA::Status', None, 1),
+
+    #Special cases for when a Control Register Access is dependent on
+    #a combination of bitfield indices (handles MTCO & MFCO)
+    'CP0_RD_SEL': ('ControlReg', 'uw', 'RD << 3 | SEL', None, 1),
+
+    #MT Control Regs
+    'MVPConf0': ('ControlReg', 'uw', 'MipsISA::MVPConf0', None, 1),
+    'MVPControl': ('ControlReg', 'uw', 'MipsISA::MVPControl', None, 1),
+    'TCBind': ('ControlReg', 'uw', 'MipsISA::TCBind', None, 1),
+    'TCStatus': ('ControlReg', 'uw', 'MipsISA::TCStatus', None, 1),
+    'TCRestart': ('ControlReg', 'uw', 'MipsISA::TCRestart', None, 1),
+    'VPEConf0': ('ControlReg', 'uw', 'MipsISA::VPEConf0', None, 1),
+    'VPEControl': ('ControlReg', 'uw', 'MipsISA::VPEControl', None, 1),
+    'YQMask': ('ControlReg', 'uw', 'MipsISA::YQMask', None, 1),
+
+    # named bitfields of Control Regs
+    'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1),
+    'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
+    'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
+    'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4),
+    'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3),
+
+    # named bitfields of Debug Regs
+    'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
+    'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1),
+
     #Memory Operand
     'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
 
     #Program Counter Operands
-    'NPC': ('NPC', 'uw', None, ( None, None, 'IsControl' ), 4),
-    'NNPC':('NNPC', 'uw', None, ( None, None, 'IsControl' ), 4)
+    'NPC': ('NPC', 'uw', None, 'IsControl', 4),
+    'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
 }};