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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-20 20:14:15 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-20 20:14:15 -0700 |
| commit | 5161bc19d9ce5199ec48a6f57c4d058a6db6cb15 (patch) | |
| tree | 06bd63f9edf9b5f28dbac29dfa60f0d9056a2004 /src/arch/mips/isa/operands.isa | |
| parent | 225de2eaff57bdf27d367531f25a654e4cd06fe6 (diff) | |
| download | gem5-5161bc19d9ce5199ec48a6f57c4d058a6db6cb15.tar.xz | |
MIPS: Use BitUnions instead of bits() functions and constants.
Also fix style issues in regions around these changes.
Diffstat (limited to 'src/arch/mips/isa/operands.isa')
| -rw-r--r-- | src/arch/mips/isa/operands.isa | 39 |
1 files changed, 2 insertions, 37 deletions
diff --git a/src/arch/mips/isa/operands.isa b/src/arch/mips/isa/operands.isa index c2733be9d..1af8857cc 100644 --- a/src/arch/mips/isa/operands.isa +++ b/src/arch/mips/isa/operands.isa @@ -140,43 +140,8 @@ def operands {{ 'Config1': ('ControlReg','uw', 'MipsISA::Config1',None,1), 'Config2': ('ControlReg','uw', 'MipsISA::Config2',None,1), 'PageGrain': ('ControlReg','uw', 'MipsISA::PageGrain',None,1), - - - # named bitfields of Control Regs - 'Status_IE': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_ERL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_EXL': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_BEV': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_CU3': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_CU2': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_CU1': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'Status_CU0': ('ControlBitfield', 'uw', 'MipsISA::Status', None, 1), - 'SRSCtl_HSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), - 'SRSCtl_PSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), - 'SRSCtl_CSS': ('ControlBitfield', 'uw', 'MipsISA::SRSCtl', None, 4), - 'Config_AR': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 3), - 'Config_MT': ('ControlBitfield', 'uw', 'MipsISA::Config', None, 1), - 'Config1_CA': ('ControlBitfield', 'uw', 'MipsISA::Config1', None, 1), - 'Config3_SP': ('ControlBitfield', 'uw', 'MipsISA::Config3', None, 1), - 'PageGrain_ESP': ('ControlBitfield', 'uw', 'MipsISA::PageGrain', None, 1), - 'Cause_EXCCODE': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), - 'Cause_TI': ('ControlBitfield', 'uw', 'MipsISA::Cause', None, 4), - 'IntCtl_IPTI': ('ControlBitfield', 'uw', 'MipsISA::IntCtl', None, 4), - 'EntryHi_ASID': ('ControlBitfield', 'uw', 'MipsISA::EntryHi', None, 1), - 'EntryLo0_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), - 'EntryLo0_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 3), - 'EntryLo0_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), - 'EntryLo0_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), - 'EntryLo0_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo0', None, 1), - 'EntryLo1_PFN': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), - 'EntryLo1_C': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 3), - 'EntryLo1_D': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), - 'EntryLo1_V': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), - 'EntryLo1_G': ('ControlBitfield', 'uw', 'MipsISA::EntryLo1', None, 1), - - # named bitfields of Debug Regs - 'Debug_DM': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), - 'Debug_IEXI': ('ControlBitfield', 'uw', 'MipsISA::Debug', None, 1), + 'Debug': ('ControlReg','uw', 'MipsISA::Debug',None,1), + 'Cause': ('ControlReg','uw', 'MipsISA::Cause',None,1), #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), |