diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
| commit | 219c423f1fb0f9a559bfa87f9812426d5e2c3e29 (patch) | |
| tree | 7980ae867c4642e710af7cd5d0ad7fe51c0b6687 /src/arch/mips/isa | |
| parent | a830e63de71e5929b8ff8e334bc872faa9193a8b (diff) | |
| download | gem5-219c423f1fb0f9a559bfa87f9812426d5e2c3e29.tar.xz | |
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/base.isa | 4 | ||||
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 18 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/mt.isa | 2 |
3 files changed, 12 insertions, 12 deletions
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa index cd6faf0f3..455ed70e7 100644 --- a/src/arch/mips/isa/base.isa +++ b/src/arch/mips/isa/base.isa @@ -72,11 +72,11 @@ output decoder {{ void MipsStaticInst::printReg(std::ostream &os, int reg) const { - if (reg < FP_Base_DepTag) { + if (reg < FP_Reg_Base) { ccprintf(os, "r%d", reg); } else { - ccprintf(os, "f%d", reg - FP_Base_DepTag); + ccprintf(os, "f%d", reg - FP_Reg_Base); } } diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 1091e67a0..5ff23ca5e 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -385,7 +385,7 @@ decode OPCODE_HI default Unknown::unknown() { 0x8: decode MT_U { 0x0: mftc0({{ data = xc->readRegOtherThread((RT << 3 | SEL) + - Ctrl_Base_DepTag); + Misc_Reg_Base); }}); 0x1: decode SEL { 0x0: mftgpr({{ @@ -409,19 +409,19 @@ decode OPCODE_HI default Unknown::unknown() { } 0x2: decode MT_H { 0x0: mftc1({{ data = xc->readRegOtherThread(RT + - FP_Base_DepTag); + FP_Reg_Base); }}); 0x1: mfthc1({{ data = xc->readRegOtherThread(RT + - FP_Base_DepTag); + FP_Reg_Base); }}); } 0x3: cftc1({{ uint32_t fcsr_val = xc->readRegOtherThread(FLOATREG_FCSR + - FP_Base_DepTag); + FP_Reg_Base); switch (RT) { case 0: data = xc->readRegOtherThread(FLOATREG_FIR + - Ctrl_Base_DepTag); + Misc_Reg_Base); break; case 25: data = (fcsr_val & 0xFE000000 >> 24) | @@ -450,7 +450,7 @@ decode OPCODE_HI default Unknown::unknown() { format MT_MTTR { // Decode MIPS MT MTTR instruction into sub-instructions 0xC: decode MT_U { - 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Ctrl_Base_DepTag, + 0x0: mttc0({{ xc->setRegOtherThread((RD << 3 | SEL) + Misc_Reg_Base, Rt); }}); 0x1: decode SEL { @@ -496,10 +496,10 @@ decode OPCODE_HI default Unknown::unknown() { } 0x2: mttc1({{ uint64_t data = xc->readRegOtherThread(RD + - FP_Base_DepTag); + FP_Reg_Base); data = insertBits(data, MT_H ? 63 : 31, MT_H ? 32 : 0, Rt); - xc->setRegOtherThread(RD + FP_Base_DepTag, + xc->setRegOtherThread(RD + FP_Reg_Base, data); }}); 0x3: cttc1({{ @@ -534,7 +534,7 @@ decode OPCODE_HI default Unknown::unknown() { "Access to Floating Control " "S""tatus Register", FS); } - xc->setRegOtherThread(FLOATREG_FCSR + FP_Base_DepTag, data); + xc->setRegOtherThread(FLOATREG_FCSR + FP_Reg_Base, data); }}); default: CP0Unimpl::unknown(); } diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa index b4d00454e..74163eebf 100644 --- a/src/arch/mips/isa/formats/mt.isa +++ b/src/arch/mips/isa/formats/mt.isa @@ -102,7 +102,7 @@ output exec {{ MVPConf0Reg &mvp_conf0) { vpe_conf0 = xc->readMiscReg(MISCREG_VPE_CONF0); - tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Ctrl_Base_DepTag); + tc_bind_mt = xc->readRegOtherThread(MISCREG_TC_BIND + Misc_Reg_Base); tc_bind = xc->readMiscReg(MISCREG_TC_BIND); vpe_control = xc->readMiscReg(MISCREG_VPE_CONTROL); mvp_conf0 = xc->readMiscReg(MISCREG_MVP_CONF0); |