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| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-03-23 08:50:57 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2010-03-23 08:50:57 -0700 |
| commit | 4d77ea7a5783d1de87a8eb804b17a6ef352998ce (patch) | |
| tree | fbf1fd950e46885fdca93abbaf689f5131752995 /src/arch/mips/isa | |
| parent | d484e1b334c6fd3f2721a2a4628c2324ed14fd08 (diff) | |
| download | gem5-4d77ea7a5783d1de87a8eb804b17a6ef352998ce.tar.xz | |
cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData())
after initiating a timing translation was causing crashes,
since a failed translation could delete the traceData
object before returning.
It turns out that there was never a need to access traceData
after initiating the translation, as the traced data was
always available earlier; this ordering was merely
historical. Furthermore, traceData->setAddress() and
traceData->setData() were being called both from the CPU
model and the ISA definition, often redundantly.
This patch standardizes all setAddress and setData calls
for memory instructions to be in the CPU models and not
in the ISA definition. It also moves those calls above
the translation calls to eliminate the crashes.
Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/formats/mem.isa | 8 | ||||
| -rw-r--r-- | src/arch/mips/isa/formats/util.isa | 3 |
2 files changed, 0 insertions, 11 deletions
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index 161a52b06..411cc5fda 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -305,7 +305,6 @@ def template StoreExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } } if (fault == NoFault) { @@ -342,7 +341,6 @@ def template StoreFPExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } } if (fault == NoFault) { @@ -377,7 +375,6 @@ def template StoreCondExecute {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, &write_result); - if (traceData) { traceData->setData(Mem); } } if (fault == NoFault) { @@ -411,7 +408,6 @@ def template StoreInitiateAcc {{ if (fault == NoFault) { fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA, memAccessFlags, NULL); - if (traceData) { traceData->setData(Mem); } } return fault; @@ -435,8 +431,6 @@ def template StoreCompleteAcc {{ if (fault == NoFault) { %(op_wb)s; - - if (traceData) { traceData->setData(getMemData(xc, pkt)); } } return fault; @@ -459,8 +453,6 @@ def template StoreCompleteAcc {{ if (fault == NoFault) { %(op_wb)s; - - if (traceData) { traceData->setData(getMemData(xc, pkt)); } } return fault; diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa index a6edffeda..708338074 100644 --- a/src/arch/mips/isa/formats/util.isa +++ b/src/arch/mips/isa/formats/util.isa @@ -38,9 +38,6 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, mem_flags = makeList(mem_flags) inst_flags = makeList(inst_flags) - # add hook to get effective addresses into execution trace output. - ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n' - # Some CPU models execute the memory operation as an atomic unit, # while others want to separate them into an effective address # computation and a memory access operation. As a result, we need |