SE/FS: Use the new FullSystem constant where possible.

6 files changed, 18 insertions, 16 deletions

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 7b8dafdba..25b470972 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
                 format BasicOp {
                     0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
                     0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
-                    0x4: decode FULL_SYSTEM {
+                    0x4: decode FullSystem {
                         0: syscall_se({{ xc->syscall(R2); }},
                                 IsSerializeAfter, IsNonSpeculative);
                         default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x0: add({{
                             IntReg result;
                             Rd = result = Rs + Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, Rt)) {
                                 fault = new IntegerOverflowFault();
                             }
@@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
                         0x2: sub({{
                             IntReg result;
                             Rd = result = Rs - Rt;
-                            if (FULL_SYSTEM &&
+                            if (FullSystem &&
                                     findOverflow(32, result, Rs, ~Rt)) {
                                 fault = new IntegerOverflowFault();
                             }
@@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
             0x0: addi({{
                 IntReg result;
                 Rt = result = Rs + imm;
-                if (FULL_SYSTEM &&
+                if (FullSystem &&
                         findOverflow(32, result, Rs, imm)) {
                     fault = new IntegerOverflowFault();
                 }
@@ -2433,7 +2433,7 @@ decode OPCODE_HI default Unknown::unknown() {
                     }
                 }
                 0x3: decode OP default FailUnimpl::rdhwr() {
-                    0x0: decode FULL_SYSTEM {
+                    0x0: decode FullSystem {
                         0: decode RD {
                             29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
                         }
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 7e90ed3e5..2d6748c05 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -128,7 +128,7 @@ def template ControlTLBExecute {{
             %(op_decl)s;
             %(op_rd)s;
 
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 if (isCoprocessor0Enabled(xc)) {
                     if(isMMUTLB(xc)){
                         %(code)s;
@@ -176,7 +176,7 @@ output exec {{
         bool
         isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
         {
-            if (!FULL_SYSTEM)
+            if (!FullSystem)
                 return true;
 
             MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@ output exec {{
         bool inline
         isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
         {
-            if (FULL_SYSTEM) {
+            if (FullSystem) {
                 MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
                 MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
                 // In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@ output exec {{
         isMMUTLB(%(CPU_exec_context)s *xc)
         {
             MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
-            return FULL_SYSTEM && (Config & 0x380) == 0x80;
+            return FullSystem && (Config & 0x380) == 0x80;
         }
 }};
 
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 2eeefe806..b288b7b20 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -143,7 +143,7 @@ output exec {{
     bool
     isDspEnabled(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
     }
 }};
 
@@ -151,7 +151,7 @@ output exec {{
     bool
     isDspPresent(%(CPU_exec_context)s *xc)
     {
-        return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+        return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
     }
 }};
 
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index f99d2327e..63823f404 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -174,7 +174,7 @@ def template FloatingPointExecute {{
 
                 //When is the right time to reset cause bits?
                 //start of every instruction or every cycle?
-                if (FULL_SYSTEM)
+                if (FullSystem)
                     fpResetCauseBits(xc);
                 %(op_decl)s;
                 %(op_rd)s;
@@ -191,7 +191,7 @@ def template FloatingPointExecute {{
                     //Check for IEEE 754 FP Exceptions
                     //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
                     bool invalid_op = false;
-                    if (FULL_SYSTEM) {
+                    if (FullSystem) {
                         invalid_op =
                             fpInvalidOp((FPOp*)this, xc, Fd, traceData);
                     }
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 65b4425af..d567a113f 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -193,7 +193,7 @@ output exec {{
     CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 0))
                 return new CoprocessorUnusableFault(0);
             else
@@ -210,7 +210,7 @@ output exec {{
     CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 1))
                 return new CoprocessorUnusableFault(1);
             else
@@ -227,7 +227,7 @@ output exec {{
     CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
-        if (FULL_SYSTEM) {
+        if (FullSystem) {
             if (!isCoprocessorEnabled(xc, 2))
                 return new CoprocessorUnusableFault(2);
             else
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index c9f5da41d..944254d90 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -58,6 +58,7 @@ output decoder {{
 #include "base/cprintf.hh"
 #include "cpu/thread_context.hh"
 #include "mem/packet.hh"
+#include "sim/full_system.hh"
 #if defined(linux)
 #include <fenv.h>
 #endif
@@ -90,6 +91,7 @@ output exec {{
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "sim/eventq.hh"
+#include "sim/full_system.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"