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| author | Gabe Black <gblack@eecs.umich.edu> | 2007-07-31 17:34:08 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2007-07-31 17:34:08 -0700 |
| commit | 4bdabe1254a8ad9bb960f57eb35cec919b370de8 (patch) | |
| tree | 318b34065ed9eb3f30852fee11eb398a92134652 /src/arch/mips/isa | |
| parent | 55ade789d34e541cc538c7c5a4f286a313cfd8ba (diff) | |
| download | gem5-4bdabe1254a8ad9bb960f57eb35cec919b370de8.tar.xz | |
Add a flag to indicate an instruction triggers a syscall in SE mode.
--HG--
extra : convert_revision : 1d0b3afdd8254f5b2fb4bbff1fa4a0536f78bb06
Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index e55d2e070..40ea223f6 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -134,7 +134,8 @@ decode OPCODE_HI default Unknown::unknown() { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 0x4: syscall({{ xc->syscall(R2); }}, - IsSerializeAfter, IsNonSpeculative); + IsSerializeAfter, IsNonSpeculative, + IsSyscall); 0x7: sync({{ ; }}, IsMemBarrier); } |