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| author | Korey Sewell <ksewell@umich.edu> | 2007-11-14 06:24:47 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2007-11-14 06:24:47 -0500 |
| commit | 5f7879a9352985775abef9515e216591a2e3e39d (patch) | |
| tree | 3aa829a03969e0694f914e7e28c597504956a59c /src/arch/mips/isa | |
| parent | bfdd2f379b89654b15f8634d405666f623d336f2 (diff) | |
| download | gem5-5f7879a9352985775abef9515e216591a2e3e39d.tar.xz | |
Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world
--HG--
extra : convert_revision : 0944e7661934baddca1f1a895af0b75be2d96b10
Diffstat (limited to 'src/arch/mips/isa')
| -rw-r--r-- | src/arch/mips/isa/formats/control.isa | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa index 4593aa52b..1671b9ad7 100644 --- a/src/arch/mips/isa/formats/control.isa +++ b/src/arch/mips/isa/formats/control.isa @@ -183,22 +183,22 @@ output decoder {{ output exec {{ bool isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) { +#if !FULL_SYSTEM + return true; +#else MiscReg Stat = xc->readMiscReg(MipsISA::Status); switch(cop_num) { case 0: { -#if FULL_SYSTEM - MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); - if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible - && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible - && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode - // Unable to use Status_CU0, etc directly, using bitfields & masks - return false; - } -#else - //printf("Syscall Emulation Mode: CP0 Enable Check defaults to TRUE\n"); -#endif + MiscReg Dbg = xc->readMiscReg(MipsISA::Debug); + if((Stat & 0x10000006) == 0 // EXL, ERL or CU0 set, CP0 accessible + && (Dbg & 0x40000000) == 0 // DM bit set, CP0 accessible + && (Stat & 0x00000018) != 0) { // KSU = 0, kernel mode is base mode + // Unable to use Status_CU0, etc directly, using bitfields & masks + return false; + } + } break; case 1: @@ -217,6 +217,7 @@ output exec {{ break; } return true; +#endif } bool inline isCoprocessor0Enabled(%(CPU_exec_context)s *xc) { |