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authorSteve Reinhardt <stever@eecs.umich.edu>2006-12-17 23:09:36 -0800
committerSteve Reinhardt <stever@eecs.umich.edu>2006-12-17 23:09:36 -0800
commitd19d7aa8a55cd4413ab00de69deb237d89d5ef4a (patch)
treedb697d8110e815ed928fac3cf674ff0bb0220e0f /src/arch/mips/isa
parent968048f56a5f866b267ad9961cbe8d16788bcc89 (diff)
downloadgem5-d19d7aa8a55cd4413ab00de69deb237d89d5ef4a.tar.xz
Minor cleanup of new snippet/subst code.
--HG-- extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
Diffstat (limited to 'src/arch/mips/isa')
-rw-r--r--src/arch/mips/isa/decoder.isa39
-rw-r--r--src/arch/mips/isa/formats/int.isa7
2 files changed, 21 insertions, 25 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index d65e3eb94..12f36c449 100644
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -154,19 +154,20 @@ decode OPCODE_HI default Unknown::unknown() {
0x3: decode FUNCTION_LO {
format HiLoOp {
- 0x0: mult({{ val = Rs.sd * Rt.sd; }});
- 0x1: multu({{ val = Rs.ud * Rt.ud; }});
- }
-
- format HiLoMiscOp {
- 0x2: div({{ if (Rt.sd != 0) {
- HI = Rs.sd % Rt.sd;
- LO = Rs.sd / Rt.sd;
+ 0x0: mult({{ int64_t val = Rs.sd * Rt.sd; }});
+ 0x1: multu({{ uint64_t val = Rs.ud * Rt.ud; }});
+ 0x2: div({{ int64_t val;
+ if (Rt.sd != 0) {
+ int64_t hi = Rs.sd % Rt.sd;
+ int64_t lo = Rs.sd / Rt.sd;
+ val = (hi << 32) | lo;
}
}});
- 0x3: divu({{ if (Rt.ud != 0) {
- HI = Rs.ud % Rt.ud;
- LO = Rs.ud / Rt.ud;
+ 0x3: divu({{ uint64_t val;
+ if (Rt.ud != 0) {
+ uint64_t hi = Rs.ud % Rt.ud;
+ uint64_t lo = Rs.ud / Rt.ud;
+ val = (hi << 32) | lo;
}
}});
}
@@ -950,17 +951,17 @@ decode OPCODE_HI default Unknown::unknown() {
}});
format HiLoOp {
- 0x0: madd({{ val = ((int64_t) HI << 32 | LO) +
- (Rs.sd * Rt.sd);
+ 0x0: madd({{ int64_t val = ((int64_t) HI << 32 | LO) +
+ (Rs.sd * Rt.sd);
}});
- 0x1: maddu({{ val = ((uint64_t) HI << 32 | LO) +
- (Rs.ud * Rt.ud);
+ 0x1: maddu({{ uint64_t val = ((uint64_t) HI << 32 | LO) +
+ (Rs.ud * Rt.ud);
}});
- 0x4: msub({{ val = ((int64_t) HI << 32 | LO) -
- (Rs.sd * Rt.sd);
+ 0x4: msub({{ int64_t val = ((int64_t) HI << 32 | LO) -
+ (Rs.sd * Rt.sd);
}});
- 0x5: msubu({{ val = ((uint64_t) HI << 32 | LO) -
- (Rs.ud * Rt.ud);
+ 0x5: msubu({{ uint64_t val = ((uint64_t) HI << 32 | LO) -
+ (Rs.ud * Rt.ud);
}});
}
}
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index e9b096f56..2f131f6d9 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -240,11 +240,6 @@ def format IntImmOp(code, *opt_flags) {{
}};
def format HiLoOp(code, *opt_flags) {{
- if '.sd' in code:
- code = 'int64_t ' + code
- elif '.ud' in code:
- code = 'uint64_t ' + code
-
code += 'HI = val<63:32>;\n'
code += 'LO = val<31:0>;\n'
@@ -260,7 +255,7 @@ def format HiLoMiscOp(code, *opt_flags) {{
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
- exec_output = HiLoExecute.subst(iop)
+ exec_output = BasicExecute.subst(iop)
}};