mips import pt. 1

src/arch/mips/SConscript:
    "mips import pt.1".

--HG--
extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1

1 files changed, 171 insertions, 19 deletions

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index f85fc5bea..5ab6957a3 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -60,24 +60,13 @@ namespace MipsISA
 
     // Constants Related to the number of registers
     const int NumIntArchRegs = 32;
-    const int NumIntSpecialRegs = 2;
+    const int NumIntSpecialRegs = 9;
     const int NumFloatArchRegs = 32;
     const int NumFloatSpecialRegs = 5;
-    const int NumControlRegs = 265;
-    const int NumInternalProcRegs = 0;
-
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-    const int NumMiscRegs = NumControlRegs;
-
-    const int TotalNumRegs = NumIntRegs + NumFloatRegs +
-    NumMiscRegs + 0/*NumInternalProcRegs*/;
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
 
     // Static instruction parameters
-    const int MaxInstSrcRegs = 3;
-    const int MaxInstDestRegs = 2;
+    const int MaxInstSrcRegs = 5;
+    const int MaxInstDestRegs = 4;
 
     // semantically meaningful register indices
     const int ZeroReg = 0;
@@ -97,7 +86,7 @@ namespace MipsISA
     const int ReturnAddressReg = 31;
 
     const int SyscallNumReg = ReturnValueReg1;
-    const int SyscallPseudoReturnReg = ReturnValueReg1;
+    const int SyscallPseudoReturnReg = ReturnValueReg2;
     const int SyscallSuccessReg = ArgumentReg3;
 
     const int LogVMPageSize = 13;	// 8K bytes
@@ -110,13 +99,176 @@ namespace MipsISA
     const int HalfwordBytes = 2;
     const int ByteBytes = 1;
 
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = 34;
-    const int Ctrl_Base_DepTag = 257;
-
     const int ANNOTE_NONE = 0;
     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
+    // Enumerate names for 'Control' Registers in the CPU
+    // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
+    // (Register Number-Register Select) Summary of Register
+    //------------------------------------------------------
+    // The first set of names classify the CP0 names as Register Banks
+    // for easy indexing when using the 'RD + SEL' index combination
+    // in CP0 instructions.
+    enum MiscRegTags {
+        Index = 0,       //Bank 0: 0 - 3
+        MVPControl,
+        MVPConf0,
+        MVPConf1,
+
+        Random = 8,      //Bank 1: 8 - 15
+        VPEControl,
+        VPEConf0,
+        VPEConf1,
+        YQMask,
+        VPESchedule,
+        VPEScheFBack,
+        VPEOpt,
+
+        EntryLo0 = 16,   //Bank 2: 16 - 23
+        TCStatus,
+        TCBind,
+        TCRestart,
+        TCHalt,
+        TCContext,
+        TCSchedule,
+        TCScheFBack,
+
+        EntryLo1 = 24,   // Bank 3: 24
+
+        Context = 32,    // Bank 4: 32 - 33
+        ContextConfig,
+
+        //PageMask = 40, //Bank 5: 40 - 41
+        PageGrain = 41,
+
+        Wired = 48,          //Bank 6:48-55
+        SRSConf0,
+        SRSConf1,
+        SRSConf2,
+        SRSConf3,
+        SRSConf4,
+
+        HWRena = 56,         //Bank 7: 56-63
+
+        BadVAddr = 64,       //Bank 8: 64-71
+
+        Count = 72,          //Bank 9: 72-79
+
+        EntryHi = 80,        //Bank 10: 80-87
+
+        Compare = 88,        //Bank 11: 88-95
+
+        Status = 96,         //Bank 12: 96-103
+        IntCtl,
+        SRSCtl,
+        SRSMap,
+
+        Cause = 104,         //Bank 13: 104-111
+
+        EPC = 112,           //Bank 14: 112-119
+
+        PRId = 120,          //Bank 15: 120-127,
+        EBase,
+
+        Config = 128,        //Bank 16: 128-135
+        Config1,
+        Config2,
+        Config3,
+        Config4,
+        Config5,
+        Config6,
+        Config7,
+
+
+        LLAddr = 136,        //Bank 17: 136-143
+
+        WatchLo0 = 144,      //Bank 18: 144-151
+        WatchLo1,
+        WatchLo2,
+        WatchLo3,
+        WatchLo4,
+        WatchLo5,
+        WatchLo6,
+        WatchLo7,
+
+        WatchHi0 = 152,     //Bank 19: 152-159
+        WatchHi1,
+        WatchHi2,
+        WatchHi3,
+        WatchHi4,
+        WatchHi5,
+        WatchHi6,
+        WatchHi7,
+
+        XCContext64 = 160, //Bank 20: 160-167
+
+                           //Bank 21: 168-175
+
+                           //Bank 22: 176-183
+
+        Debug = 184,       //Bank 23: 184-191
+        TraceControl1,
+        TraceControl2,
+        UserTraceData,
+        TraceBPC,
+
+        DEPC = 192,        //Bank 24: 192-199
+
+        PerfCnt0 = 200,    //Bank 25: 200-207
+        PerfCnt1,
+        PerfCnt2,
+        PerfCnt3,
+        PerfCnt4,
+        PerfCnt5,
+        PerfCnt6,
+        PerfCnt7,
+
+        ErrCtl = 208,      //Bank 26: 208-215
+
+        CacheErr0 = 216,   //Bank 27: 216-223
+        CacheErr1,
+        CacheErr2,
+        CacheErr3,
+
+        TagLo0 = 224,      //Bank 28: 224-231
+        DataLo1,
+        TagLo2,
+        DataLo3,
+        TagLo4,
+        DataLo5,
+        TagLo6,
+        DataLo7,
+
+        TagHi0 = 232,      //Bank 29: 232-239
+        DataHi1,
+        TagHi2,
+        DataHi3,
+        TagHi4,
+        DataHi5,
+        TagHi6,
+        DataHi7,
+
+
+        ErrorEPC = 240,    //Bank 30: 240-247
+
+        DESAVE = 248,       //Bank 31: 248-256
+
+        LLFlag = 257,
+
+        NumControlRegs
+    };
+
+    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
+    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
+    const int NumMiscRegs = NumControlRegs;
+
+    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
+
+    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
+
+    // These help enumerate all the registers for dependence tracking.
+    const int FP_Base_DepTag = NumIntRegs;
+    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 };
 
 using namespace MipsISA;