Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

1 files changed, 0 insertions, 213 deletions

diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 7522dcf0f..a8d5b07b6 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -143,7 +143,6 @@ namespace MipsISA
         NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
     };
 
-
     // MIPS modes
     enum mode_type
     {
@@ -154,53 +153,9 @@ namespace MipsISA
         mode_number             // number of modes
     };
 
-  inline mode_type getOperatingMode(MiscReg Stat)
-  {
-    if((Stat & 0x10000006) != 0 || (Stat & 0x18) ==0)
-      return mode_kernel;
-    else{
-      if((Stat & 0x18) == 0x8)
-        return mode_supervisor;
-      else if((Stat & 0x18) == 0x10)
-        return mode_user;
-      else return mode_number;
-    }
-  }
-
-
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
-    // Constants Related to the number of registers
-    const int NumIntArchRegs = 32;
-    const int NumIntSpecialRegs = 9;
-    const int NumFloatArchRegs = 32;
-    const int NumFloatSpecialRegs = 5;
-
-    const int MaxShadowRegSets = 16; // Maximum number of shadow register sets
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;        //HI & LO Regs
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;//
-
-    // Static instruction parameters
-    const int MaxInstSrcRegs = 10;
-    const int MaxInstDestRegs = 8;
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;
-    const int AssemblerReg = 1;
-    const int SyscallSuccessReg = 7;
-    const int FirstArgumentReg = 4;
-    const int ReturnValueReg = 2;
-
-    const int KernelReg0 = 26;
-    const int KernelReg1 = 27;
-    const int GlobalPointerReg = 28;
-    const int StackPointerReg = 29;
-    const int FramePointerReg = 30;
-    const int ReturnAddressReg = 31;
-
-    const int SyscallPseudoReturnReg = 3;
-
     const int LogVMPageSize = 13;       // 8K bytes
     const int VMPageSize = (1 << LogVMPageSize);
 
@@ -213,174 +168,6 @@ namespace MipsISA
 
     const int ANNOTE_NONE = 0;
     const uint32_t ITOUCH_ANNOTE = 0xffffffff;
-
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
-
-    // Enumerate names for 'Control' Registers in the CPU
-    // Reference MIPS32 Arch. for Programmers, Vol. III, Ch.8
-    // (Register Number-Register Select) Summary of Register
-    //------------------------------------------------------
-    // The first set of names classify the CP0 names as Register Banks
-    // for easy indexing when using the 'RD + SEL' index combination
-    // in CP0 instructions.
-    enum MiscRegTags {
-        Index = Ctrl_Base_DepTag + 0,       //Bank 0: 0 - 3
-        MVPControl,
-        MVPConf0,
-        MVPConf1,
-
-        CP0_Random = Ctrl_Base_DepTag + 8,      //Bank 1: 8 - 15
-        VPEControl,
-        VPEConf0,
-        VPEConf1,
-        YQMask,
-        VPESchedule,
-        VPEScheFBack,
-        VPEOpt,
-
-        EntryLo0 = Ctrl_Base_DepTag + 16,   //Bank 2: 16 - 23
-        TCStatus,
-        TCBind,
-        TCRestart,
-        TCHalt,
-        TCContext,
-        TCSchedule,
-        TCScheFBack,
-
-        EntryLo1 = Ctrl_Base_DepTag + 24,   // Bank 3: 24
-
-        Context = Ctrl_Base_DepTag + 32,    // Bank 4: 32 - 33
-        ContextConfig,
-
-        PageMask = Ctrl_Base_DepTag + 40, //Bank 5: 40 - 41
-        PageGrain = Ctrl_Base_DepTag + 41,
-
-        Wired = Ctrl_Base_DepTag + 48,          //Bank 6:48-55
-        SRSConf0,
-        SRSConf1,
-        SRSConf2,
-        SRSConf3,
-        SRSConf4,
-
-        HWRena = Ctrl_Base_DepTag + 56,         //Bank 7: 56-63
-
-        BadVAddr = Ctrl_Base_DepTag + 64,       //Bank 8: 64-71
-
-        Count = Ctrl_Base_DepTag + 72,          //Bank 9: 72-79
-
-        EntryHi = Ctrl_Base_DepTag + 80,        //Bank 10: 80-87
-
-        Compare = Ctrl_Base_DepTag + 88,        //Bank 11: 88-95
-
-        Status = Ctrl_Base_DepTag + 96,         //Bank 12: 96-103
-        IntCtl,
-        SRSCtl,
-        SRSMap,
-
-        Cause = Ctrl_Base_DepTag + 104,         //Bank 13: 104-111
-
-        EPC = Ctrl_Base_DepTag + 112,           //Bank 14: 112-119
-
-        PRId = Ctrl_Base_DepTag + 120,          //Bank 15: 120-127,
-        EBase,
-
-        Config = Ctrl_Base_DepTag + 128,        //Bank 16: 128-135
-        Config1,
-        Config2,
-        Config3,
-        Config4,
-        Config5,
-        Config6,
-        Config7,
-
-
-        LLAddr = Ctrl_Base_DepTag + 136,        //Bank 17: 136-143
-
-        WatchLo0 = Ctrl_Base_DepTag + 144,      //Bank 18: 144-151
-        WatchLo1,
-        WatchLo2,
-        WatchLo3,
-        WatchLo4,
-        WatchLo5,
-        WatchLo6,
-        WatchLo7,
-
-        WatchHi0 = Ctrl_Base_DepTag + 152,     //Bank 19: 152-159
-        WatchHi1,
-        WatchHi2,
-        WatchHi3,
-        WatchHi4,
-        WatchHi5,
-        WatchHi6,
-        WatchHi7,
-
-        XCContext64 = Ctrl_Base_DepTag + 160, //Bank 20: 160-167
-
-                           //Bank 21: 168-175
-
-                           //Bank 22: 176-183
-
-        Debug = Ctrl_Base_DepTag + 184,       //Bank 23: 184-191
-        TraceControl1,
-        TraceControl2,
-        UserTraceData,
-        TraceBPC,
-
-        DEPC = Ctrl_Base_DepTag + 192,        //Bank 24: 192-199
-
-        PerfCnt0 = Ctrl_Base_DepTag + 200,    //Bank 25: 200-207
-        PerfCnt1,
-        PerfCnt2,
-        PerfCnt3,
-        PerfCnt4,
-        PerfCnt5,
-        PerfCnt6,
-        PerfCnt7,
-
-        ErrCtl = Ctrl_Base_DepTag + 208,      //Bank 26: 208-215
-
-        CacheErr0 = Ctrl_Base_DepTag + 216,   //Bank 27: 216-223
-        CacheErr1,
-        CacheErr2,
-        CacheErr3,
-
-        TagLo0 = Ctrl_Base_DepTag + 224,      //Bank 28: 224-231
-        DataLo1,
-        TagLo2,
-        DataLo3,
-        TagLo4,
-        DataLo5,
-        TagLo6,
-        DataLo7,
-
-        TagHi0 = Ctrl_Base_DepTag + 232,      //Bank 29: 232-239
-        DataHi1,
-        TagHi2,
-        DataHi3,
-        TagHi4,
-        DataHi5,
-        TagHi6,
-        DataHi7,
-
-
-        ErrorEPC = Ctrl_Base_DepTag + 240,    //Bank 30: 240-247
-
-        DESAVE = Ctrl_Base_DepTag + 248,       //Bank 31: 248-256
-
-        LLFlag = Ctrl_Base_DepTag + 257,
-
-        NumControlRegs
-    };
-
-    const int TotalDataRegs = NumIntRegs + NumFloatRegs;
-
-    const int NumMiscRegs = NumControlRegs;
-
-    const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
-
-
 };
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__